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[76.183.134.35]) by smtp.gmail.com with ESMTPSA id z4sm7336864otu.24.2022.02.22.11.14.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 11:14:38 -0800 (PST) Date: Tue, 22 Feb 2022 13:14:37 -0600 From: Chris Morgan To: Robin Murphy Cc: Heiko =?iso-8859-1?Q?St=FCbner?= , devicetree@vger.kernel.org, robh+dt@kernel.org, jon.lin@rock-chips.com, linux-rockchip@lists.infradead.org, Chris Morgan Subject: Re: [PATCH] arm64: dts: rockchip: Correct clock-output-names for rk817 Message-ID: <20220222191437.GA7995@wintermute.localdomain> References: <20220216165837.4721-1-macroalpha82@gmail.com> <44462609.a43xROnmBz@diego> <4b88f0f1-7422-7beb-2f7a-563f1f4b3360@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <4b88f0f1-7422-7beb-2f7a-563f1f4b3360@arm.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Feb 16, 2022 at 09:34:52PM +0000, Robin Murphy wrote: > On 2022-02-16 20:42, Heiko Stübner wrote: > > Hi, > > > > Am Mittwoch, 16. Februar 2022, 17:58:37 CET schrieb Chris Morgan: > > > From: Chris Morgan > > > > > > According to the datasheet for the rk817 there is only a single output > > > clock for the PMIC. I don't believe this is causing any harm though > > > and testing this change doesn't appear to have any noticeable effects. > > > > hmm, looking at the go2's schematics, I'd disagree: > > > > - yes, the rk817 has only one clock output > > - but no, it is used for the clkout_32k signal, which gets piped back into > > the SoC. As that clock dynamically appears at some unspecified point > > when the rk817 probes, the clock controller expects it to be named > > xin32k to bind into its clock-tree. > > > > The driver (drivers/clk/clk-rk808.c) really puts that rk817-clk32k at > > position 2 but I'm not sure if that simply papers over some implementation > > Indeed it appears to be a hangover from RK808 where CLK32KOUT1 is always-on > and CLK32KOUT2 is the switchable one. It's even more obvious on RK805 which > still shares the original control register layout. > > Robin. Okay, so I'm thinking for now we cancel this patch, note in the yaml updates patch series that this issue is present, update the driver, and then notify the board dts maintainers to switch over and test. Does that sound good? Thank you. > > > > > > > Heiko > > > > > Signed-off-by: Chris Morgan > > > --- > > > arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts > > > index ea0695b51ecd..5b23e607876e 100644 > > > --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts > > > +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts > > > @@ -296,7 +296,7 @@ rk817: pmic@20 { > > > reg = <0x20>; > > > interrupt-parent = <&gpio0>; > > > interrupts = ; > > > - clock-output-names = "rk808-clkout1", "xin32k"; > > > + clock-output-names = "rk808-clkout1"; > > > clock-names = "mclk"; > > > clocks = <&cru SCLK_I2S1_OUT>; > > > pinctrl-names = "default"; > > > > > > > > > > > > > > > _______________________________________________ > > Linux-rockchip mailing list > > Linux-rockchip@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-rockchip