[PATCH v2 0/4] arm64: dts: rockchip: add usb3 support to rk356x

[PATCH v2 0/4] arm64: dts: rockchip: add usb3 support to rk356x

[Michael Riesch]

Hi all,

This series introduces the USB 3.0 xHCI controller nodes and enables
them on the RK3568 EVB1. USB 3.0 host and gadget operation have been
tested successfully.

The second version of the series considers Johan's comments which
helped a lot to clean things up and get rid of the dtbs_check issues.

Looking forward to your comments!

Best regards,
Michael

Changes since v1:
- move power domain PD_PIPE to rk356x
- add rockchip,rk3568-dwc3 compatible to documentation
- merge subnodes with corresponding nodes
- remove all quirks (add at a later stage if required)

Michael Riesch (4):
  arm64: dts: rockchip: move power domain PD_PIPE to rk356x
  dt-bindings: usb: add rk3568 compatible to rockchip,dwc3
  arm64: dts: rockchip: add the usb3 nodes to rk356x
  arm64: dts: rockchip: add usb3 support to rk3568-evb1-v10

 .../bindings/usb/rockchip,dwc3.yaml           |  2 +
 .../boot/dts/rockchip/rk3568-evb1-v10.dts     | 46 +++++++++++++++++++
 arch/arm64/boot/dts/rockchip/rk3568.dtsi      | 17 ++-----
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      | 44 ++++++++++++++++++
 4 files changed, 95 insertions(+), 14 deletions(-)

-- 
2.30.2

[PATCH v2 1/4] arm64: dts: rockchip: move power domain PD_PIPE to rk356x

[Michael Riesch]

The power domain PD_PIPE was moved to the RK3568 specific dtsi but
is available on the RK3566 as well. Move it back to the shared dtsi.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi | 16 ----------------
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 14 ++++++++++++++
 2 files changed, 14 insertions(+), 16 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 91a0b798b857..ecc0f3015915 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -100,19 +100,3 @@ opp-1992000000 {
 		opp-microvolt = <1150000 1150000 1150000>;
 	};
 };
-
-&power {
-	power-domain@RK3568_PD_PIPE {
-		reg = <RK3568_PD_PIPE>;
-		clocks = <&cru PCLK_PIPE>;
-		pm_qos = <&qos_pcie2x1>,
-			 <&qos_pcie3x1>,
-			 <&qos_pcie3x2>,
-			 <&qos_sata0>,
-			 <&qos_sata1>,
-			 <&qos_sata2>,
-			 <&qos_usb3_0>,
-			 <&qos_usb3_1>;
-		#power-domain-cells = <0>;
-	};
-};
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 8b9fae3d348a..742f5adcdf2b 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -490,6 +490,20 @@ power-domain@RK3568_PD_RKVENC {
 					 <&qos_rkvenc_wr_m0>;
 				#power-domain-cells = <0>;
 			};
+
+			power-domain@RK3568_PD_PIPE {
+				reg = <RK3568_PD_PIPE>;
+				clocks = <&cru PCLK_PIPE>;
+				pm_qos = <&qos_pcie2x1>,
+					 <&qos_pcie3x1>,
+					 <&qos_pcie3x2>,
+					 <&qos_sata0>,
+					 <&qos_sata1>,
+					 <&qos_sata2>,
+					 <&qos_usb3_0>,
+					 <&qos_usb3_1>;
+				#power-domain-cells = <0>;
+			};
 		};
 	};
 
-- 
2.30.2

Re: [PATCH v2 1/4] arm64: dts: rockchip: move power domain PD_PIPE to rk356x

[Robin Murphy]

On 2022-02-25 13:15, Michael Riesch wrote:
> The power domain PD_PIPE was moved to the RK3568 specific dtsi but
> is available on the RK3566 as well. Move it back to the shared dtsi.

Note that a corresponding definition does already exist in rk3568.dtsi. 
That one *could* inherit the base definition and only override the 
"pm_qos" property, but looking back to the original patch series it 
seems like not doing that was a deliberate choice.

Robin.

> Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
> ---
>   arch/arm64/boot/dts/rockchip/rk3568.dtsi | 16 ----------------
>   arch/arm64/boot/dts/rockchip/rk356x.dtsi | 14 ++++++++++++++
>   2 files changed, 14 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index 91a0b798b857..ecc0f3015915 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -100,19 +100,3 @@ opp-1992000000 {
>   		opp-microvolt = <1150000 1150000 1150000>;
>   	};
>   };
> -
> -&power {
> -	power-domain@RK3568_PD_PIPE {
> -		reg = <RK3568_PD_PIPE>;
> -		clocks = <&cru PCLK_PIPE>;
> -		pm_qos = <&qos_pcie2x1>,
> -			 <&qos_pcie3x1>,
> -			 <&qos_pcie3x2>,
> -			 <&qos_sata0>,
> -			 <&qos_sata1>,
> -			 <&qos_sata2>,
> -			 <&qos_usb3_0>,
> -			 <&qos_usb3_1>;
> -		#power-domain-cells = <0>;
> -	};
> -};
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index 8b9fae3d348a..742f5adcdf2b 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -490,6 +490,20 @@ power-domain@RK3568_PD_RKVENC {
>   					 <&qos_rkvenc_wr_m0>;
>   				#power-domain-cells = <0>;
>   			};
> +
> +			power-domain@RK3568_PD_PIPE {
> +				reg = <RK3568_PD_PIPE>;
> +				clocks = <&cru PCLK_PIPE>;
> +				pm_qos = <&qos_pcie2x1>,
> +					 <&qos_pcie3x1>,
> +					 <&qos_pcie3x2>,
> +					 <&qos_sata0>,
> +					 <&qos_sata1>,
> +					 <&qos_sata2>,
> +					 <&qos_usb3_0>,
> +					 <&qos_usb3_1>;
> +				#power-domain-cells = <0>;
> +			};
>   		};
>   	};
>   

Re: [PATCH v2 1/4] arm64: dts: rockchip: move power domain PD_PIPE to rk356x

[Michael Riesch]

Hi Robin,

On 2/25/22 15:14, Robin Murphy wrote:
> On 2022-02-25 13:15, Michael Riesch wrote:
>> The power domain PD_PIPE was moved to the RK3568 specific dtsi but
>> is available on the RK3566 as well. Move it back to the shared dtsi.
> 
> Note that a corresponding definition does already exist in rk3568.dtsi.
> That one *could* inherit the base definition and only override the
> "pm_qos" property, but looking back to the original patch series it
> seems like not doing that was a deliberate choice.

OK, my bad. I overlooked that both rk3566 and rk3568 have their
definition in their dtsi files, so there is no need for this patch.
Sorry for the confusion!

Best regards,
Michael

> 
> Robin.
> 
>> Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
>> ---
>>   arch/arm64/boot/dts/rockchip/rk3568.dtsi | 16 ----------------
>>   arch/arm64/boot/dts/rockchip/rk356x.dtsi | 14 ++++++++++++++
>>   2 files changed, 14 insertions(+), 16 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
>> b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
>> index 91a0b798b857..ecc0f3015915 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
>> @@ -100,19 +100,3 @@ opp-1992000000 {
>>           opp-microvolt = <1150000 1150000 1150000>;
>>       };
>>   };
>> -
>> -&power {
>> -    power-domain@RK3568_PD_PIPE {
>> -        reg = <RK3568_PD_PIPE>;
>> -        clocks = <&cru PCLK_PIPE>;
>> -        pm_qos = <&qos_pcie2x1>,
>> -             <&qos_pcie3x1>,
>> -             <&qos_pcie3x2>,
>> -             <&qos_sata0>,
>> -             <&qos_sata1>,
>> -             <&qos_sata2>,
>> -             <&qos_usb3_0>,
>> -             <&qos_usb3_1>;
>> -        #power-domain-cells = <0>;
>> -    };
>> -};
>> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
>> b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
>> index 8b9fae3d348a..742f5adcdf2b 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
>> @@ -490,6 +490,20 @@ power-domain@RK3568_PD_RKVENC {
>>                        <&qos_rkvenc_wr_m0>;
>>                   #power-domain-cells = <0>;
>>               };
>> +
>> +            power-domain@RK3568_PD_PIPE {
>> +                reg = <RK3568_PD_PIPE>;
>> +                clocks = <&cru PCLK_PIPE>;
>> +                pm_qos = <&qos_pcie2x1>,
>> +                     <&qos_pcie3x1>,
>> +                     <&qos_pcie3x2>,
>> +                     <&qos_sata0>,
>> +                     <&qos_sata1>,
>> +                     <&qos_sata2>,
>> +                     <&qos_usb3_0>,
>> +                     <&qos_usb3_1>;
>> +                #power-domain-cells = <0>;
>> +            };
>>           };
>>       };
>>   

Re: [PATCH v2 1/4] arm64: dts: rockchip: move power domain PD_PIPE to rk356x

[Johan Jonker]

Hi Michael,

Some more comments. Have a look if it's useful.

On 2/25/22 14:15, Michael Riesch wrote:
> The power domain PD_PIPE was moved to the RK3568 specific dtsi but
> is available on the RK3566 as well. Move it back to the shared dtsi.
> 
> Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
> ---
>  arch/arm64/boot/dts/rockchip/rk3568.dtsi | 16 ----------------
>  arch/arm64/boot/dts/rockchip/rk356x.dtsi | 14 ++++++++++++++
>  2 files changed, 14 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index 91a0b798b857..ecc0f3015915 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -100,19 +100,3 @@ opp-1992000000 {
>  		opp-microvolt = <1150000 1150000 1150000>;
>  	};
>  };

> -
> -&power {
> -	power-domain@RK3568_PD_PIPE {
> -		reg = <RK3568_PD_PIPE>;
> -		clocks = <&cru PCLK_PIPE>;

Should contain a complete list of rk3568 clocks for which RK3568_PD_PIPE
must be enabled.

Could someone check which we need here?
Same for rk3566 but then reduced.

<&cru PCLK_PIPE>,

<&cru PCLK_XPCS>,

<&cru CLK_USB3OTG0_REF>,
<&cru CLK_USB3OTG0_SUSPEND>,
<&cru ACLK_USB3OTG0>,

<&cru CLK_USB3OTG1_REF>,
<&cru CLK_USB3OTG1_SUSPEND>,
<&cru ACLK_USB3OTG1>,

<&cru ACLK_SATA0>,
<&cru CLK_SATA0_PMALIVE>,
<&cru CLK_SATA0_RXOOB>

<&cru ACLK_SATA1>,
<&cru CLK_SATA1_PMALIVE>,
<&cru CLK_SATA1_RXOOB>,

<&cru ACLK_SATA2>,
<&cru CLK_SATA2_PMALIVE>,
<&cru CLK_SATA2_RXOOB>

<&cru ACLK_PCIE20_MST>,
<&cru ACLK_PCIE20_SLV>,
<&cru ACLK_PCIE20_DBI>,
<&cru PCLK_PCIE20>,
<&cru CLK_PCIE20_AUX_NDFT>

<&cru ACLK_PCIE30X1_MST>,
<&cru ACLK_PCIE30X1_SLV>,
<&cru ACLK_PCIE30X1_DBI>,
<&cru PCLK_PCIE30X1>,
<&cru CLK_PCIE30X1_AUX_NDFT>

<&cru ACLK_PCIE30X2_MST>,
<&cru ACLK_PCIE30X2_SLV>,
<&cru ACLK_PCIE30X2_DBI>,
<&cru PCLK_PCIE30X2>,
<&cru CLK_PCIE30X2_AUX_NDFT>;

> -		pm_qos = <&qos_pcie2x1>,
> -			 <&qos_pcie3x1>,
> -			 <&qos_pcie3x2>,
> -			 <&qos_sata0>,
> -			 <&qos_sata1>,
> -			 <&qos_sata2>,
> -			 <&qos_usb3_0>,
> -			 <&qos_usb3_1>;
> -		#power-domain-cells = <0>;
> -	};

Maybe keep it here for rk3568.

> -};
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index 8b9fae3d348a..742f5adcdf2b 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -490,6 +490,20 @@ power-domain@RK3568_PD_RKVENC {
>  					 <&qos_rkvenc_wr_m0>;
>  				#power-domain-cells = <0>;
>  			};

> +
> +			power-domain@RK3568_PD_PIPE {
> +				reg = <RK3568_PD_PIPE>;

> +				clocks = <&cru PCLK_PIPE>;
> +				pm_qos = <&qos_pcie2x1>,
> +					 <&qos_pcie3x1>,
> +					 <&qos_pcie3x2>,
> +					 <&qos_sata0>,
> +					 <&qos_sata1>,
> +					 <&qos_sata2>,
> +					 <&qos_usb3_0>,
> +					 <&qos_usb3_1>;
> +				#power-domain-cells = <0>;
> +			};

rk3566 doesn't have a combphy0
Already in rk3566.dtsi

&power {
	power-domain@RK3568_PD_PIPE {
		reg = <RK3568_PD_PIPE>;

		clocks = <&cru PCLK_PIPE>;


Should contain a complete list of rk3566 clocks for which RK3568_PD_PIPE
must be enabled.

		pm_qos = <&qos_pcie2x1>,
			 <&qos_sata1>,
			 <&qos_sata2>,

			 <&qos_usb3_0>,

Does rk3566 have a qos_usb3_0 ??
See support list below.

			 <&qos_usb3_1>;
		#power-domain-cells = <0>;
	};
};

===

Rockchip RK3568 Datasheet V1.0-20201210.pdf page 16

Multi-PHY0 support one of the following interfaces
USB3.0 OTG
SATA0

Multi-PHY1 support one of the following interfaces
USB3.0 Host
SATA1
QSGMII/SGMII

Multi-PHY2 support one of the following interfaces
PCIe2.1
SATA2
QSGMII/SGMII

===

Rockchip RK3566 Datasheet V1.0-20201210.pdf page 16

Multi-PHY1 support one of the following interfaces
USB3.0 Host
SATA1

Multi-PHY2 support one of the following interfaces
PCIe2.1
SATA2

===

https://eji4evk5kxx.exactdn.com/wp-content/uploads/2020/12/RK3568-multiplexed-sata-usb-3.0-pcie.jpg?lossy=1&ssl=1


On rk3568:
&usb_host0_xhci {
	phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
	phy-names = "usb2-phy", "usb3-phy";
};

Does this exists on rk3566?

&usb_host0_xhci {
	phys = <&usb2phy0_otg>;
	phy-names = "usb2-phy";
};

If not then why is usb_host0_xhci in a common rk356x.dtsi ??
Else fix rk3566.dtsi

===

Johan



>  		};
>  	};
>  

[PATCH v2 2/4] dt-bindings: usb: add rk3568 compatible to rockchip,dwc3

[Michael Riesch]

Add the compatible for the Rockchip RK3568 variant.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
---
 Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
index 04077f2d7faf..b3798d94d2fd 100644
--- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
@@ -30,6 +30,7 @@ select:
         enum:
           - rockchip,rk3328-dwc3
           - rockchip,rk3399-dwc3
+          - rockchip,rk3568-dwc3
   required:
     - compatible
 
@@ -39,6 +40,7 @@ properties:
       - enum:
           - rockchip,rk3328-dwc3
           - rockchip,rk3399-dwc3
+          - rockchip,rk3568-dwc3
       - const: snps,dwc3
 
   reg:
-- 
2.30.2

Re: [PATCH v2 2/4] dt-bindings: usb: add rk3568 compatible to rockchip,dwc3

[Rob Herring]

On Fri, 25 Feb 2022 14:16:00 +0100, Michael Riesch wrote:
> Add the compatible for the Rockchip RK3568 variant.
> 
> Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
> ---
>  Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH v2 3/4] arm64: dts: rockchip: add the usb3 nodes to rk356x

[Michael Riesch]

The Rockchip RK3566 and RK3568 feature two USB 3.0 xHCI controllers,
one of them with Dual Role Device (DRD) capability.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi |  5 ++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 30 ++++++++++++++++++++++++
 2 files changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index ecc0f3015915..25f6398e5a66 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -100,3 +100,8 @@ opp-1992000000 {
 		opp-microvolt = <1150000 1150000 1150000>;
 	};
 };
+
+&usb_host0_xhci {
+	phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
+	phy-names = "usb2-phy", "usb3-phy";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 742f5adcdf2b..9ea6f551b9f4 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -230,6 +230,36 @@ scmi_shmem: sram@0 {
 		};
 	};
 
+	usb_host0_xhci: usb@fcc00000 {
+		compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
+		reg = <0x0 0xfcc00000 0x0 0x400000>;
+		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
+			 <&cru ACLK_USB3OTG0>;
+		clock-names = "ref_clk", "suspend_clk", "bus_clk";
+		dr_mode = "otg";
+		phy_type = "utmi_wide";
+		power-domains = <&power RK3568_PD_PIPE>;
+		resets = <&cru SRST_USB3OTG0>;
+		status = "disabled";
+	};
+
+	usb_host1_xhci: usb@fd000000 {
+		compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
+		reg = <0x0 0xfd000000 0x0 0x400000>;
+		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
+			 <&cru ACLK_USB3OTG1>;
+		clock-names = "ref_clk", "suspend_clk", "bus_clk";
+		dr_mode = "host";
+		phy_type = "utmi_wide";
+		phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
+		phy-names = "usb2-phy", "usb3-phy";
+		power-domains = <&power RK3568_PD_PIPE>;
+		resets = <&cru SRST_USB3OTG1>;
+		status = "disabled";
+	};
+
 	gic: interrupt-controller@fd400000 {
 		compatible = "arm,gic-v3";
 		reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
-- 
2.30.2

[PATCH v2 4/4] arm64: dts: rockchip: add usb3 support to rk3568-evb1-v10

[Michael Riesch]

The Rockchip RK3568 EVB1 features one USB 3.0 device-only
(USB 2.0 OTG) port and one USB 3.0 host-only port.
Activate the USB 3.0 controller nodes and phy nodes in the
device tree.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
---
 .../boot/dts/rockchip/rk3568-evb1-v10.dts     | 46 +++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
index a794a0ea5c70..622be8be9813 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
@@ -103,6 +103,18 @@ vcc5v0_usb_host: vcc5v0-usb-host {
 		vin-supply = <&vcc5v0_usb>;
 	};
 
+	vcc5v0_usb_otg: vcc5v0-usb-otg {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en>;
+		regulator-name = "vcc5v0_usb_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
 	vcc3v3_lcd0_n: vcc3v3-lcd0-n {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc3v3_lcd0_n";
@@ -136,6 +148,14 @@ regulator-state-mem {
 	};
 };
 
+&combphy0 {
+	status = "okay";
+};
+
+&combphy1 {
+	status = "okay";
+};
+
 &cpu0 {
 	cpu-supply = <&vdd_cpu>;
 };
@@ -507,6 +527,9 @@ usb {
 		vcc5v0_usb_host_en: vcc5v0_usb_host_en {
 			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+		vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
 	};
 };
 
@@ -568,6 +591,11 @@ &usb_host0_ohci {
 	status = "okay";
 };
 
+&usb_host0_xhci {
+	extcon = <&usb2phy0>;
+	status = "okay";
+};
+
 &usb_host1_ehci {
 	status = "okay";
 };
@@ -576,6 +604,24 @@ &usb_host1_ohci {
 	status = "okay";
 };
 
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	vbus-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
 &usb2phy1 {
 	status = "okay";
 };
-- 
2.30.2