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From: Sudeep Holla <sudeep.holla@arm.com>
To: Shawn Guo <shawn.guo@linaro.org>
Cc: Marc Zyngier <maz@kernel.org>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Valentin Schneider <valentin.schneider@arm.com>,
	Sudeep Holla <sudeep.holla@arm.com>,
	Sebastian Andrzej Siewior <bigeasy@linutronix.de>,
	Thomas Gleixner <tglx@linutronix.de>,
	Maulik Shah <quic_mkshah@quicinc.com>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Ulf Hansson <ulf.hansson@linaro.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v6 1/3] PM: cpu: Add CPU_LAST_PM_ENTER and CPU_FIRST_PM_EXIT support
Date: Fri, 25 Feb 2022 14:20:36 +0000	[thread overview]
Message-ID: <20220225142036.cxh7u24wljgwu3od@bogus> (raw)
In-Reply-To: <20220225043311.GB269879@dragon>

On Fri, Feb 25, 2022 at 12:33:11PM +0800, Shawn Guo wrote:
> On Wed, Feb 23, 2022 at 07:30:50PM +0000, Sudeep Holla wrote:
> > On Wed, Feb 23, 2022 at 08:55:34PM +0800, Shawn Guo wrote:
> > > It becomes a common situation on some platforms that certain hardware
> > > setup needs to be done on the last standing cpu, and rpmh-rsc[1] is such
> > > an existing example.  As figuring out the last standing cpu is really
> > > something generic, it adds CPU_LAST_PM_ENTER (and CPU_FIRST_PM_EXIT)
> > > event support to cpu_pm helper, so that individual driver can be
> > > notified when the last standing cpu is about to enter low power state.
> > 
> > Sorry for not getting back on the previous email thread.
> > When I meant I didn't want to use CPU_CLUSTER_PM_{ENTER,EXIT}, I wasn't
> > thinking new ones to be added as alternative. With this OSI cpuidle, we
> > have introduces the concept of power domains and I was check if we can
> > associate these requirements to them rather than introducing the first
> > and last cpu notion. The power domains already identify them in order
> > to turn on or off. Not sure if there is any notification mechanism in
> > genpd/power domains. I really don't like this addition. It is disintegrating
> > all the solutions for OSI and makes it hard to understand.
> > 
> > One solution I can think of(not sure if others like or if that is feasible)
> > is to create a parent power domain that encloses all the last level CPU
> > power domains, which means when the last one is getting powered off, you
> > will be asked to power off and you can take whatever action you want.
> 
> Thanks Sudeep for the input!  Yes, it works for me (if I understand your
> suggestion correctly).  So the needed changes on top of the current
> version would be:
> 
> 1) Declare MPM as a PD (power domain) provider and have it be the
>    parent PD of cpu cluster (the platform has only one cluster including
>    4 cpus).
> 

[...]

> 
> Let's me know if this is what you are asking for, thanks!

Matches exactly. I don't know if there is anything I am missing to see,
but if this possible, for me it is easier to understand as this is all
linked to power-domains like other things in OSI cpuidle.

So yes, I prefer this, but let us see what others have to say about this.

-- 
Regards,
Sudeep

  reply	other threads:[~2022-02-25 14:21 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-23 12:55 [PATCH v6 0/3] Add Qualcomm MPM irqchip driver support Shawn Guo
2022-02-23 12:55 ` [PATCH v6 1/3] PM: cpu: Add CPU_LAST_PM_ENTER and CPU_FIRST_PM_EXIT support Shawn Guo
2022-02-23 19:30   ` Sudeep Holla
2022-02-25  4:33     ` Shawn Guo
2022-02-25 14:20       ` Sudeep Holla [this message]
2022-02-23 12:55 ` [PATCH v6 2/3] dt-bindings: interrupt-controller: Add Qualcomm MPM support Shawn Guo
2022-02-23 12:55 ` [PATCH v6 3/3] irqchip: Add Qualcomm MPM controller driver Shawn Guo
2022-02-23 23:43   ` kernel test robot
2022-02-24  2:10     ` Shawn Guo
2022-02-25  8:54       ` Marc Zyngier
2022-05-04 14:08 ` [PATCH v6 0/3] Add Qualcomm MPM irqchip driver support Ulf Hansson
2022-05-04 19:21   ` Sudeep Holla

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