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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id z23-20020aa79597000000b004e1bf2f5818sm15915098pfj.87.2022.02.28.20.11.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 20:11:53 -0800 (PST) Date: Tue, 1 Mar 2022 12:11:47 +0800 From: Shawn Guo To: Bhupesh Sharma Cc: linux-arm-msm@vger.kernel.org, bhupesh.linux@gmail.com, agross@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, vkoul@kernel.org, linux-phy@lists.infradead.org, robh+dt@kernel.org, Bjorn Andersson , Rob Herring Subject: Re: [PATCH v2 6/8] arm64: dts: qcom: ipq6018: Fix qmp usb3 phy node Message-ID: <20220301041147.GI269879@dragon> References: <20220228123019.382037-1-bhupesh.sharma@linaro.org> <20220228123019.382037-7-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220228123019.382037-7-bhupesh.sharma@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Feb 28, 2022 at 06:00:17PM +0530, Bhupesh Sharma wrote: > Fix the following 'make dtbs_check' warning(s) by > using phy@ instead of lanes@ and by moving '#clock-names' to s/clock-names/clock-cells > sub-node: > > arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml: ssphy@78000: > 'lane@78200' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' > > Cc: Bjorn Andersson > Cc: Rob Herring > Signed-off-by: Bhupesh Sharma Other than that: Reviewed-by: Shawn Guo > --- > arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi > index 66ec5615651d..ad7914e49532 100644 > --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi > @@ -674,7 +674,6 @@ ssphy_0: ssphy@78000 { > reg = <0x0 0x78000 0x0 0x1C4>; > #address-cells = <2>; > #size-cells = <2>; > - #clock-cells = <1>; > ranges; > > clocks = <&gcc GCC_USB0_AUX_CLK>, > @@ -686,12 +685,13 @@ ssphy_0: ssphy@78000 { > reset-names = "phy","common"; > status = "disabled"; > > - usb0_ssphy: lane@78200 { > + usb0_ssphy: phy@78200 { > reg = <0x0 0x00078200 0x0 0x130>, /* Tx */ > <0x0 0x00078400 0x0 0x200>, /* Rx */ > <0x0 0x00078800 0x0 0x1F8>, /* PCS */ > <0x0 0x00078600 0x0 0x044>; /* PCS misc */ > #phy-cells = <0>; > + #clock-cells = <1>; > clocks = <&gcc GCC_USB0_PIPE_CLK>; > clock-names = "pipe0"; > clock-output-names = "gcc_usb0_pipe_clk_src"; > -- > 2.35.1 >