From: Michael Walle <michael@walle.cc>
To: Linus Walleij <linus.walleij@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Lars Povlsen <lars.povlsen@microchip.com>
Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Horatiu Vultur <horatiu.vultur@microchip.com>,
Michael Walle <michael@walle.cc>
Subject: [PATCH RFC v1 1/2] dt-bindings: pinctrl: ocelot: add reset property
Date: Sun, 13 Mar 2022 16:46:39 +0100 [thread overview]
Message-ID: <20220313154640.63813-2-michael@walle.cc> (raw)
In-Reply-To: <20220313154640.63813-1-michael@walle.cc>
On the LAN966x SoC the GPIO controller will be resetted together with
the SGPIO and the switch core. Add a phandle to register the shared
reset line.
Signed-off-by: Michael Walle <michael@walle.cc>
---
.../devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
index 40148aef4ecf..cc9e14a214b1 100644
--- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
@@ -42,6 +42,14 @@ properties:
"#interrupt-cells":
const: 2
+ resets:
+ maxItems: 1
+
+ reset-names:
+ description: Optional shared switch reset.
+ items:
+ - const: switch
+
required:
- compatible
- reg
--
2.30.2
next prev parent reply other threads:[~2022-03-13 15:46 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-13 15:46 [PATCH RFC v1 0/2] pinctrl: ocelot: add shared reset Michael Walle
2022-03-13 15:46 ` Michael Walle [this message]
2022-03-23 17:54 ` [PATCH RFC v1 1/2] dt-bindings: pinctrl: ocelot: add reset property Rob Herring
2022-03-13 15:46 ` [PATCH RFC v1 2/2] pinctrl: ocelot: add optional shared reset Michael Walle
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