* [PATCH 0/2] arm64: dts: add corstone1000 device tree @ 2022-03-25 13:36 Rui Miguel Silva 2022-03-25 13:36 ` [PATCH 1/2] dt-bindings: arm: add corstone1000 platform Rui Miguel Silva 2022-03-25 13:36 ` [PATCH 2/2] arm64: dts: arm: add corstone1000 device tree Rui Miguel Silva 0 siblings, 2 replies; 8+ messages in thread From: Rui Miguel Silva @ 2022-03-25 13:36 UTC (permalink / raw) To: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-kernel, devicetree, Rui Miguel Silva Add device tree and correspondent binding for ARM corstone1000 [0] platform for FVP (Fixed Virtual Platform) and FPGA MPS3 prototyping board implementation of this system. Cheers, Rui 0: https://documentation-service.arm.com/static/619e02b1f45f0b1fbf3a8f16 Rui Miguel Silva (2): dt-bindings: arm: add corstone1000 platform arm64: dts: arm: add corstone1000 device tree .../bindings/arm/arm,corstone1000.yaml | 45 ++++++ arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 31 ++++ arch/arm64/boot/dts/arm/corstone1000-mps3.dts | 38 +++++ arch/arm64/boot/dts/arm/corstone1000.dtsi | 151 ++++++++++++++++++ 5 files changed, 266 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone1000.yaml create mode 100644 arch/arm64/boot/dts/arm/corstone1000-fvp.dts create mode 100644 arch/arm64/boot/dts/arm/corstone1000-mps3.dts create mode 100644 arch/arm64/boot/dts/arm/corstone1000.dtsi -- 2.35.1 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] dt-bindings: arm: add corstone1000 platform 2022-03-25 13:36 [PATCH 0/2] arm64: dts: add corstone1000 device tree Rui Miguel Silva @ 2022-03-25 13:36 ` Rui Miguel Silva 2022-03-25 17:29 ` Krzysztof Kozlowski 2022-03-25 17:34 ` Krzysztof Kozlowski 2022-03-25 13:36 ` [PATCH 2/2] arm64: dts: arm: add corstone1000 device tree Rui Miguel Silva 1 sibling, 2 replies; 8+ messages in thread From: Rui Miguel Silva @ 2022-03-25 13:36 UTC (permalink / raw) To: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-kernel, devicetree, Rui Miguel Silva [-- Warning: decoded text below may be mangled, UTF-8 assumed --] [-- Attachment #1: Type: text/plain; charset=y, Size: 2332 bytes --] Add bindings to describe the FPGA in a prototyping board (MPS3) implementation and the Fixed Virtual Platform implementation of the ARM Corstone1000 platform. Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> --- .../bindings/arm/arm,corstone1000.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone1000.yaml diff --git a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml new file mode 100644 index 000000000000..a77f88223801 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Corstone1000 Device Tree Bindings + +maintainers: + - Vishnu Banavath <vishnu.banavath@arm.com> + - Rui Miguel Silva <rui.silva@linaro.org> + +description: |+ + ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that + provides a flexible compute architecture that combines Cortex‑A and Cortex‑M + processors. + + Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion + systems for M-Class (or other) processors for adding sensors, connectivity, + video, audio and machine learning at the edge System and security IPs to build + a secure SoC for a range of rich IoT applications, for example gateways, smart + cameras and embedded systems. + + Integrated Secure Enclave providing hardware Root of Trust and supporting + seamless integration of the optional CryptoCell™-312 cryptographic + accelerator. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA + implementation of the Corstone1000 in the MPS3 prototyping board. See + ARM document DAI0550. + items: + - const: arm,corstone1000-mps3 + - description: Corstone1000 FVP is the Fixed Virtual Platform + implementation of this system. See ARM ecosystems FVP's. + items: + - const: arm,corstone1000-fvp + +additionalProperties: true + +... -- 2.35.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] dt-bindings: arm: add corstone1000 platform 2022-03-25 13:36 ` [PATCH 1/2] dt-bindings: arm: add corstone1000 platform Rui Miguel Silva @ 2022-03-25 17:29 ` Krzysztof Kozlowski 2022-03-28 16:19 ` Rob Herring 2022-03-25 17:34 ` Krzysztof Kozlowski 1 sibling, 1 reply; 8+ messages in thread From: Krzysztof Kozlowski @ 2022-03-25 17:29 UTC (permalink / raw) To: Rui Miguel Silva, Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-kernel, devicetree On 25/03/2022 14:36, Rui Miguel Silva wrote: > Add bindings to describe the FPGA in a prototyping board > (MPS3) implementation and the Fixed Virtual Platform > implementation of the ARM Corstone1000 platform. > > Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> > --- > .../bindings/arm/arm,corstone1000.yaml | 45 +++++++++++++++++++ > 1 file changed, 45 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone1000.yaml > > diff --git a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml > new file mode 100644 > index 000000000000..a77f88223801 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml > @@ -0,0 +1,45 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ARM Corstone1000 Device Tree Bindings > + > +maintainers: > + - Vishnu Banavath <vishnu.banavath@arm.com> > + - Rui Miguel Silva <rui.silva@linaro.org> > + > +description: |+ > + ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that > + provides a flexible compute architecture that combines Cortex‑A and Cortex‑M > + processors. > + > + Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion > + systems for M-Class (or other) processors for adding sensors, connectivity, > + video, audio and machine learning at the edge System and security IPs to build > + a secure SoC for a range of rich IoT applications, for example gateways, smart > + cameras and embedded systems. > + > + Integrated Secure Enclave providing hardware Root of Trust and supporting > + seamless integration of the optional CryptoCell™-312 cryptographic > + accelerator. > + > +properties: > + $nodename: > + const: '/' > + compatible: > + oneOf: > + - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA > + implementation of the Corstone1000 in the MPS3 prototyping board. See > + ARM document DAI0550. > + items: > + - const: arm,corstone1000-mps3 If I understood correctly your description and DAI0550, the MPS3 board is a board with Corstone 100, so you miss here compatible for the chip (e.g. arm,corstone1000). I guess similar pattern for the FVP, so both should be combined within an enum (skipping all this description). Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] dt-bindings: arm: add corstone1000 platform 2022-03-25 17:29 ` Krzysztof Kozlowski @ 2022-03-28 16:19 ` Rob Herring 0 siblings, 0 replies; 8+ messages in thread From: Rob Herring @ 2022-03-28 16:19 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Rui Miguel Silva, Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Krzysztof Kozlowski, linux-arm-kernel, devicetree On Fri, Mar 25, 2022 at 06:29:05PM +0100, Krzysztof Kozlowski wrote: > On 25/03/2022 14:36, Rui Miguel Silva wrote: > > Add bindings to describe the FPGA in a prototyping board > > (MPS3) implementation and the Fixed Virtual Platform > > implementation of the ARM Corstone1000 platform. > > > > Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> > > --- > > .../bindings/arm/arm,corstone1000.yaml | 45 +++++++++++++++++++ > > 1 file changed, 45 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone1000.yaml > > > > diff --git a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml > > new file mode 100644 > > index 000000000000..a77f88223801 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml > > @@ -0,0 +1,45 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: ARM Corstone1000 Device Tree Bindings > > + > > +maintainers: > > + - Vishnu Banavath <vishnu.banavath@arm.com> > > + - Rui Miguel Silva <rui.silva@linaro.org> > > + > > +description: |+ > > + ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that > > + provides a flexible compute architecture that combines Cortex‑A and Cortex‑M > > + processors. > > + > > + Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion > > + systems for M-Class (or other) processors for adding sensors, connectivity, > > + video, audio and machine learning at the edge System and security IPs to build > > + a secure SoC for a range of rich IoT applications, for example gateways, smart > > + cameras and embedded systems. > > + > > + Integrated Secure Enclave providing hardware Root of Trust and supporting > > + seamless integration of the optional CryptoCell™-312 cryptographic > > + accelerator. > > + > > +properties: > > + $nodename: > > + const: '/' > > + compatible: > > + oneOf: > > + - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA > > + implementation of the Corstone1000 in the MPS3 prototyping board. See > > + ARM document DAI0550. > > + items: > > + - const: arm,corstone1000-mps3 > > If I understood correctly your description and DAI0550, the MPS3 board > is a board with Corstone 100, so you miss here compatible for the chip > (e.g. arm,corstone1000). > > I guess similar pattern for the FVP, so both should be combined within > an enum (skipping all this description). Corstone1000 is a collection of IP that would be the basis for an SoC. These 2 are FVP and FPGA implementations of corstone1000 with additional IP to make them usable (e.g. USB and ethernet). Each one as a whole is a one off AIUI. So I don't think they really fit into our board plus SoC compatible patten and are fine as-is. Rob ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] dt-bindings: arm: add corstone1000 platform 2022-03-25 13:36 ` [PATCH 1/2] dt-bindings: arm: add corstone1000 platform Rui Miguel Silva 2022-03-25 17:29 ` Krzysztof Kozlowski @ 2022-03-25 17:34 ` Krzysztof Kozlowski 1 sibling, 0 replies; 8+ messages in thread From: Krzysztof Kozlowski @ 2022-03-25 17:34 UTC (permalink / raw) To: Rui Miguel Silva, Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-kernel, devicetree On 25/03/2022 14:36, Rui Miguel Silva wrote: > Add bindings to describe the FPGA in a prototyping board > (MPS3) implementation and the Fixed Virtual Platform > implementation of the ARM Corstone1000 platform. > > Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> > --- > .../bindings/arm/arm,corstone1000.yaml | 45 +++++++++++++++++++ > 1 file changed, 45 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone1000.yaml > > diff --git a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml > new file mode 100644 > index 000000000000..a77f88223801 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml > @@ -0,0 +1,45 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ARM Corstone1000 Device Tree Bindings > + > +maintainers: > + - Vishnu Banavath <vishnu.banavath@arm.com> > + - Rui Miguel Silva <rui.silva@linaro.org> > + > +description: |+ > + ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that > + provides a flexible compute architecture that combines Cortex‑A and Cortex‑M > + processors. > + > + Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion > + systems for M-Class (or other) processors for adding sensors, connectivity, > + video, audio and machine learning at the edge System and security IPs to build > + a secure SoC for a range of rich IoT applications, for example gateways, smart > + cameras and embedded systems. > + > + Integrated Secure Enclave providing hardware Root of Trust and supporting > + seamless integration of the optional CryptoCell™-312 cryptographic > + accelerator. > + > +properties: > + $nodename: > + const: '/' > + compatible: > + oneOf: > + - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA > + implementation of the Corstone1000 in the MPS3 prototyping board. See > + ARM document DAI0550. > + items: > + - const: arm,corstone1000-mps3 If I understood correctly your description and DAI0550, the MPS3 board is a board with Corstone 100, so you miss here compatible for the chip (e.g. arm,corstone1000). I guess similar pattern for the FVP, so both should be combined within an enum (skipping all this description). Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/2] arm64: dts: arm: add corstone1000 device tree 2022-03-25 13:36 [PATCH 0/2] arm64: dts: add corstone1000 device tree Rui Miguel Silva 2022-03-25 13:36 ` [PATCH 1/2] dt-bindings: arm: add corstone1000 platform Rui Miguel Silva @ 2022-03-25 13:36 ` Rui Miguel Silva 2022-03-25 17:46 ` Rob Herring 2022-03-28 16:35 ` Marc Zyngier 1 sibling, 2 replies; 8+ messages in thread From: Rui Miguel Silva @ 2022-03-25 13:36 UTC (permalink / raw) To: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-kernel, devicetree, Rui Miguel Silva Corstone1000 is a platform from arm, which includes pre verified Corstone SSE710 sub-system that combines Cortex-A and Cortex-M processors [0]. These device trees contains the necessary bits to support the Corstone 1000 FVP (Fixed Virtual Platform) [1] and the FPGA MPS3 board Cortex-A35 implementation at Cortex-A35 host side of this platform. [2] 0: https://documentation-service.arm.com/static/619e02b1f45f0b1fbf3a8f16 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps 2: https://documentation-service.arm.com/static/61f3f4d7fa8173727a1b71bf Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> --- arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 31 ++++ arch/arm64/boot/dts/arm/corstone1000-mps3.dts | 38 +++++ arch/arm64/boot/dts/arm/corstone1000.dtsi | 151 ++++++++++++++++++ 4 files changed, 221 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/corstone1000-fvp.dts create mode 100644 arch/arm64/boot/dts/arm/corstone1000-mps3.dts create mode 100644 arch/arm64/boot/dts/arm/corstone1000.dtsi diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index 4382b73baef5..d908e96d7ddc 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb ju dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts new file mode 100644 index 000000000000..8f6ce94b4d5a --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000.dtsi" + +/ { + model = "ARM Corstone1000 FVP (Fixed Virtual Platform)"; + compatible = "arm,corstone1000-fvp"; + + ethernet: eth@4010000 { + compatible = "smsc,lan91c111"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 116 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + reg-io-width = <2>; + smsc,irq-push-pull; + }; + +}; + +&refclk { + clock-frequency = <50000000>; +}; diff --git a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts new file mode 100644 index 000000000000..922253f0af07 --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000.dtsi" + +/ { + model = "ARM Corstone1000 FPGA MPS3 board"; + compatible = "arm,corstone1000-mps3"; + + ethernet: eth@4010000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <2>; + smsc,irq-push-pull; + }; + + usb: usb@40200000 { + compatible = "nxp,usb-isp1763"; + reg = <0x40200000 0x100000>; + interrupts-parent = <&gic>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + bus-width = <16>; + dr_mode = "host"; + }; +}; + +&refclk { + clock-frequency = <50000000>; +}; diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi new file mode 100644 index 000000000000..eb423af84e9f --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + stdout-path = "/uart@1a510000:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0>; + next-level-cache = <&L2_0>; + }; + }; + + memory@88200000 { + device_type = "memory"; + reg = <0x88200000 0x77e00000>; + }; + + gic: interrupt-controller@1c000000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1c010000 0x1000>, + <0x1c02f000 0x2000>, + <0x1c04f000 0x1000>, + <0x1c06f000 0x2000>; + interrupts = <1 9 0xf08>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + + refclk100mhz: refclk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "apb_pclk"; + }; + + smbclk: refclk24mhzx2 { + /* Reference 24MHz clock x 2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "smclk"; + }; + + uartclk: uartclk { + /* UART clock - 50MHz */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "uartclk"; + }; + + serial0: uart@1a510000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a510000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + refclk: refclk@1a220000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x1a220000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@1a230000 { + frame-number = <0>; + interrupts = <GIC_SPI 2 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1a230000 0x1000>; + }; + }; + + mbox_es0mhu0: mhu@1b000000 { + compatible = "arm,mhuv2","arm,primecell"; + reg = <0x1b000000 0x1000>, + <0x1b010000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mhu_rx"; + #mbox-cells = <1>; + mbox-name = "arm-es0-mhu0"; + }; + + mbox_es0mhu1: mhu@1b020000 { + compatible = "arm,mhuv2","arm,primecell"; + reg = <0x1b020000 0x1000>, + <0x1b030000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mhu_rx"; + #mbox-cells = <1>; + mbox-name = "arm-es0-mhu1"; + }; + + mbox_semhu1: mhu@1b820000 { + compatible = "arm,mhuv2","arm,primecell"; + reg = <0x1b820000 0x1000>, + <0x1b830000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mhu_rx"; + #mbox-cells = <1>; + mbox-name = "arm-se-mhu1"; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; +}; -- 2.35.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] arm64: dts: arm: add corstone1000 device tree 2022-03-25 13:36 ` [PATCH 2/2] arm64: dts: arm: add corstone1000 device tree Rui Miguel Silva @ 2022-03-25 17:46 ` Rob Herring 2022-03-28 16:35 ` Marc Zyngier 1 sibling, 0 replies; 8+ messages in thread From: Rob Herring @ 2022-03-25 17:46 UTC (permalink / raw) To: Rui Miguel Silva Cc: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Krzysztof Kozlowski, linux-arm-kernel, devicetree On Fri, Mar 25, 2022 at 01:36:55PM +0000, Rui Miguel Silva wrote: > Corstone1000 is a platform from arm, which includes pre > verified Corstone SSE710 sub-system that combines Cortex-A and > Cortex-M processors [0]. > > These device trees contains the necessary bits to support the > Corstone 1000 FVP (Fixed Virtual Platform) [1] and the > FPGA MPS3 board Cortex-A35 implementation at Cortex-A35 host > side of this platform. [2] > > 0: https://documentation-service.arm.com/static/619e02b1f45f0b1fbf3a8f16 > 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps > 2: https://documentation-service.arm.com/static/61f3f4d7fa8173727a1b71bf > > Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> > --- > arch/arm64/boot/dts/arm/Makefile | 1 + > arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 31 ++++ > arch/arm64/boot/dts/arm/corstone1000-mps3.dts | 38 +++++ > arch/arm64/boot/dts/arm/corstone1000.dtsi | 151 ++++++++++++++++++ > 4 files changed, 221 insertions(+) > create mode 100644 arch/arm64/boot/dts/arm/corstone1000-fvp.dts > create mode 100644 arch/arm64/boot/dts/arm/corstone1000-mps3.dts > create mode 100644 arch/arm64/boot/dts/arm/corstone1000.dtsi Please run 'make dtbs_check' on these and fix any errors. > diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile > index 4382b73baef5..d908e96d7ddc 100644 > --- a/arch/arm64/boot/dts/arm/Makefile > +++ b/arch/arm64/boot/dts/arm/Makefile > @@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb ju > dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb > dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb > dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb > +dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb > diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts > new file mode 100644 > index 000000000000..8f6ce94b4d5a > --- /dev/null > +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts > @@ -0,0 +1,31 @@ > +// SPDX-License-Identifier: BSD-3-Clause While nothing is shared, the existing Arm, Ltd dts files here are GPL2 only or GPL/BSD. The preference for dts files is dual GPL2 and BSD/MIT > +/* > + * Copyright (c) 2022, Arm Limited. All rights reserved. > + * Copyright (c) 2022, Linaro Limited. All rights reserved. > + * > + */ > + > +/dts-v1/; > + > +#include "corstone1000.dtsi" > + > +/ { > + model = "ARM Corstone1000 FVP (Fixed Virtual Platform)"; > + compatible = "arm,corstone1000-fvp"; > + > + ethernet: eth@4010000 { > + compatible = "smsc,lan91c111"; > + reg = <0x40100000 0x10000>; > + phy-mode = "mii"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 116 (GIC_CPU_MASK_SIMPLE(4) | > + IRQ_TYPE_LEVEL_HIGH)>; > + reg-io-width = <2>; > + smsc,irq-push-pull; > + }; > + > +}; > + > +&refclk { > + clock-frequency = <50000000>; > +}; > diff --git a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts > new file mode 100644 > index 000000000000..922253f0af07 > --- /dev/null > +++ b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts > @@ -0,0 +1,38 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2022, Arm Limited. All rights reserved. > + * Copyright (c) 2022, Linaro Limited. All rights reserved. > + * > + */ > + > +/dts-v1/; > + > +#include "corstone1000.dtsi" > + > +/ { > + model = "ARM Corstone1000 FPGA MPS3 board"; > + compatible = "arm,corstone1000-mps3"; > + > + ethernet: eth@4010000 { > + compatible = "smsc,lan9220", "smsc,lan9115"; > + reg = <0x40100000 0x10000>; > + phy-mode = "mii"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; > + reg-io-width = <2>; > + smsc,irq-push-pull; > + }; > + > + usb: usb@40200000 { > + compatible = "nxp,usb-isp1763"; > + reg = <0x40200000 0x100000>; > + interrupts-parent = <&gic>; > + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; > + bus-width = <16>; > + dr_mode = "host"; > + }; > +}; > + > +&refclk { > + clock-frequency = <50000000>; > +}; > diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi > new file mode 100644 > index 000000000000..eb423af84e9f > --- /dev/null > +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi > @@ -0,0 +1,151 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2022, Arm Limited. All rights reserved. > + * Copyright (c) 2022, Linaro Limited. All rights reserved. > + * > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + interrupt-parent = <&gic>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + chosen { > + stdout-path = "/uart@1a510000:115200n8"; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,armv8"; This compatible is only valid for models. The FPGA should have something else. > + reg = <0>; > + next-level-cache = <&L2_0>; > + }; > + }; > + > + memory@88200000 { > + device_type = "memory"; > + reg = <0x88200000 0x77e00000>; > + }; > + > + gic: interrupt-controller@1c000000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0x1c010000 0x1000>, > + <0x1c02f000 0x2000>, > + <0x1c04f000 0x1000>, > + <0x1c06f000 0x2000>; > + interrupts = <1 9 0xf08>; > + }; > + > + L2_0: l2-cache0 { > + compatible = "cache"; > + }; > + > + refclk100mhz: refclk100mhz { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; > + clock-output-names = "apb_pclk"; > + }; > + > + smbclk: refclk24mhzx2 { > + /* Reference 24MHz clock x 2 */ > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <48000000>; > + clock-output-names = "smclk"; > + }; > + > + uartclk: uartclk { > + /* UART clock - 50MHz */ > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <50000000>; > + clock-output-names = "uartclk"; > + }; > + > + serial0: uart@1a510000 { Place nodes with an MMIO address under one (or more) simple-bus nodes. You might want that to align with what's in the the SSE710 subsystem and not in it. > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x1a510000 0x1000>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&uartclk>, <&refclk100mhz>; > + clock-names = "uartclk", "apb_pclk"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | > + IRQ_TYPE_LEVEL_LOW)>; > + }; > + > + refclk: refclk@1a220000 { refclk? > + compatible = "arm,armv7-timer-mem"; > + reg = <0x1a220000 0x1000>; 1 space ^^ > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + frame@1a230000 { > + frame-number = <0>; > + interrupts = <GIC_SPI 2 (GIC_CPU_MASK_SIMPLE(4) | > + IRQ_TYPE_LEVEL_HIGH)>; > + reg = <0x1a230000 0x1000>; > + }; > + }; > + > + mbox_es0mhu0: mhu@1b000000 { mailbox@... > + compatible = "arm,mhuv2","arm,primecell"; space ^ > + reg = <0x1b000000 0x1000>, > + <0x1b010000 0x1000>; > + clocks = <&refclk100mhz>; > + clock-names = "apb_pclk"; > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "mhu_rx"; > + #mbox-cells = <1>; > + mbox-name = "arm-es0-mhu0"; It's 'mbox-names', but that's a consumer, not provider property. You should see a warning for this. > + }; > + > + mbox_es0mhu1: mhu@1b020000 { > + compatible = "arm,mhuv2","arm,primecell"; > + reg = <0x1b020000 0x1000>, > + <0x1b030000 0x1000>; > + clocks = <&refclk100mhz>; > + clock-names = "apb_pclk"; > + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "mhu_rx"; > + #mbox-cells = <1>; > + mbox-name = "arm-es0-mhu1"; > + }; > + > + mbox_semhu1: mhu@1b820000 { > + compatible = "arm,mhuv2","arm,primecell"; > + reg = <0x1b820000 0x1000>, > + <0x1b830000 0x1000>; > + clocks = <&refclk100mhz>; > + clock-names = "apb_pclk"; > + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "mhu_rx"; > + #mbox-cells = <1>; > + mbox-name = "arm-se-mhu1"; > + }; > + > + psci { > + compatible = "arm,psci-1.0", "arm,psci-0.2"; > + method = "smc"; > + }; > +}; > -- > 2.35.1 > > ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] arm64: dts: arm: add corstone1000 device tree 2022-03-25 13:36 ` [PATCH 2/2] arm64: dts: arm: add corstone1000 device tree Rui Miguel Silva 2022-03-25 17:46 ` Rob Herring @ 2022-03-28 16:35 ` Marc Zyngier 1 sibling, 0 replies; 8+ messages in thread From: Marc Zyngier @ 2022-03-28 16:35 UTC (permalink / raw) To: Rui Miguel Silva Cc: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring, Krzysztof Kozlowski, linux-arm-kernel, devicetree On Fri, 25 Mar 2022 13:36:55 +0000, Rui Miguel Silva <rui.silva@linaro.org> wrote: > > Corstone1000 is a platform from arm, which includes pre > verified Corstone SSE710 sub-system that combines Cortex-A and > Cortex-M processors [0]. > > These device trees contains the necessary bits to support the > Corstone 1000 FVP (Fixed Virtual Platform) [1] and the > FPGA MPS3 board Cortex-A35 implementation at Cortex-A35 host > side of this platform. [2] > > 0: https://documentation-service.arm.com/static/619e02b1f45f0b1fbf3a8f16 > 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps > 2: https://documentation-service.arm.com/static/61f3f4d7fa8173727a1b71bf > > Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> > --- > arch/arm64/boot/dts/arm/Makefile | 1 + > arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 31 ++++ > arch/arm64/boot/dts/arm/corstone1000-mps3.dts | 38 +++++ > arch/arm64/boot/dts/arm/corstone1000.dtsi | 151 ++++++++++++++++++ > 4 files changed, 221 insertions(+) > create mode 100644 arch/arm64/boot/dts/arm/corstone1000-fvp.dts > create mode 100644 arch/arm64/boot/dts/arm/corstone1000-mps3.dts > create mode 100644 arch/arm64/boot/dts/arm/corstone1000.dtsi > > diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile > index 4382b73baef5..d908e96d7ddc 100644 > --- a/arch/arm64/boot/dts/arm/Makefile > +++ b/arch/arm64/boot/dts/arm/Makefile > @@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb ju > dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb > dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb > dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb > +dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb > diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts > new file mode 100644 > index 000000000000..8f6ce94b4d5a > --- /dev/null > +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts > @@ -0,0 +1,31 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2022, Arm Limited. All rights reserved. > + * Copyright (c) 2022, Linaro Limited. All rights reserved. > + * > + */ > + > +/dts-v1/; > + > +#include "corstone1000.dtsi" > + > +/ { > + model = "ARM Corstone1000 FVP (Fixed Virtual Platform)"; > + compatible = "arm,corstone1000-fvp"; > + > + ethernet: eth@4010000 { > + compatible = "smsc,lan91c111"; > + reg = <0x40100000 0x10000>; > + phy-mode = "mii"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 116 (GIC_CPU_MASK_SIMPLE(4) | > + IRQ_TYPE_LEVEL_HIGH)>; -ENOPARSE. Please read the GIC binding. > + reg-io-width = <2>; > + smsc,irq-push-pull; > + }; > + > +}; > + > +&refclk { > + clock-frequency = <50000000>; > +}; > diff --git a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts > new file mode 100644 > index 000000000000..922253f0af07 > --- /dev/null > +++ b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts [...] > + gic: interrupt-controller@1c000000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0x1c010000 0x1000>, > + <0x1c02f000 0x2000>, > + <0x1c04f000 0x1000>, > + <0x1c06f000 0x2000>; > + interrupts = <1 9 0xf08>; Why 4 CPUs? You only have 1. The rest of the file seems to use the symbolic encoding, so please pick one or the other, but don't mix them. [...] > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | > + IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | > + IRQ_TYPE_LEVEL_LOW)>; Same question. > + }; > + > + refclk: refclk@1a220000 { > + compatible = "arm,armv7-timer-mem"; > + reg = <0x1a220000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + frame@1a230000 { > + frame-number = <0>; > + interrupts = <GIC_SPI 2 (GIC_CPU_MASK_SIMPLE(4) | > + IRQ_TYPE_LEVEL_HIGH)>; This makes no sense either. M. -- Without deviation from the norm, progress is not possible. ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-03-28 16:35 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-03-25 13:36 [PATCH 0/2] arm64: dts: add corstone1000 device tree Rui Miguel Silva 2022-03-25 13:36 ` [PATCH 1/2] dt-bindings: arm: add corstone1000 platform Rui Miguel Silva 2022-03-25 17:29 ` Krzysztof Kozlowski 2022-03-28 16:19 ` Rob Herring 2022-03-25 17:34 ` Krzysztof Kozlowski 2022-03-25 13:36 ` [PATCH 2/2] arm64: dts: arm: add corstone1000 device tree Rui Miguel Silva 2022-03-25 17:46 ` Rob Herring 2022-03-28 16:35 ` Marc Zyngier
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