From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2E9DC433EF for ; Wed, 30 Mar 2022 05:12:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242804AbiC3FOT (ORCPT ); Wed, 30 Mar 2022 01:14:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242795AbiC3FOO (ORCPT ); Wed, 30 Mar 2022 01:14:14 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D37C29BAED; Tue, 29 Mar 2022 22:12:28 -0700 (PDT) X-UUID: c788adcedbfb4701b48689ef8bb3e588-20220330 X-UUID: c788adcedbfb4701b48689ef8bb3e588-20220330 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 838381258; Wed, 30 Mar 2022 13:12:19 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 30 Mar 2022 13:12:17 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Mar 2022 13:12:17 +0800 From: Miles Chen To: CC: , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v9 03/22] dt-bindings: mediatek,dp_phy: Add Display Port PHY binding Date: Wed, 30 Mar 2022 13:12:17 +0800 Message-ID: <20220330051217.19789-1-miles.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220327223927.20848-4-granquet@baylibre.com> References: <20220327223927.20848-4-granquet@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org >This phy controller is embedded in the Display Port Controller on mt8195 SoCs. > >Signed-off-by: Guillaume Ranquet >--- > .../bindings/phy/mediatek,dp-phy.yaml | 43 +++++++++++++++++++ > 1 file changed, 43 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml > >diff --git a/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml >new file mode 100644 >index 000000000000..1f5ffca4e140 >--- /dev/null >+++ b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml >@@ -0,0 +1,43 @@ >+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >+# Copyright (c) 2022 MediaTek >+%YAML 1.2 >+--- >+$id: http://devicetree.org/schemas/phy/mediatek,dp-phy.yaml# >+$schema: http://devicetree.org/meta-schemas/core.yaml# >+ >+title: MediaTek Display Port PHY >+ >+maintainers: >+ - CK Hu >+ - Jitao shi >+ >+description: | >+ Device tree bindings for the Mediatek (embedded) Display Port PHY s/Mediatek/MediaTek/ >+ present on some Mediatek SoCs. s/Mediatek/MediaTek/ >+ >+properties: >+ compatible: >+ enum: >+ - mediatek,mt8195-dp-phy >+ >+ mediatek,dp-syscon: >+ $ref: /schemas/types.yaml#/definitions/phandle >+ description: Phandle to the Display Port node. >+ >+ "#phy-cells": >+ const: 0 >+ >+required: >+ - compatible >+ - mediatek,dp-syscon >+ - "#phy-cells" >+ >+additionalProperties: false >+ >+examples: >+ - | >+ dp_phy: dp-phy { >+ compatible = "mediatek,mt8195-dp-phy"; >+ mediatek,dp-syscon = <&dp_tx>; >+ #phy-cells = <0>; >+ }; >-- >2.34.1 > >