* [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: add DP & DP PHY
2022-03-31 14:30 [PATCH v2 0/2] DSS: Add support for DisplayPort Rahul T R
@ 2022-03-31 14:30 ` Rahul T R
2022-03-31 14:30 ` [PATCH v2 2/2] arm64: dts: ti: k3-j721e-common-proc-board: add DP to j7 evm Rahul T R
1 sibling, 0 replies; 5+ messages in thread
From: Rahul T R @ 2022-03-31 14:30 UTC (permalink / raw)
To: nm
Cc: vigneshr, kristo, robh+dt, krzysztof.kozlowski, linux-arm-kernel,
devicetree, linux-kernel, tomi.valkeinen, laurent.pinchart,
kishon, r-ravikumar
From: Tomi Valkeinen <tomi.valkeinen@ti.com>
Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP
8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper.
A slight irregularity in the bindings is the DPTX PHY register block,
which is in the MHDP IP, but is needed and mapped by the PHY.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 65 +++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index db0669985e42..11426c25a09d 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -5,6 +5,7 @@
* Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-ti.h>
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/mux/ti-serdes.h>
@@ -789,6 +790,47 @@
#size-cells = <2>;
};
+ serdes_wiz4: wiz@5050000 {
+ compatible = "ti,am64-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 297 9>;
+ assigned-clock-parents = <&k3_clks 297 10>;
+ assigned-clock-rates = <19200000>;
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x5050000 0x0 0x5050000 0x10000>,
+ <0xa030a00 0x0 0xa030a00 0x40>;
+
+ serdes4: serdes@5050000 {
+ /*
+ * Note: we also map DPTX PHY registers as the Torrent
+ * needs to manage those.
+ */
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x5050000 0x10000>,
+ <0xa030a00 0x40>; /* DPTX PHY */
+ reg-names = "torrent_phy", "dptx_phy";
+
+ resets = <&serdes_wiz4 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>;
+ clock-names = "refclk";
+ assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 297 9>,
+ <&k3_clks 297 9>,
+ <&k3_clks 297 9>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
@@ -1267,6 +1309,29 @@
};
};
+ mhdp: dp-bridge@a000000 {
+ compatible = "ti,j721e-mhdp8546";
+ /*
+ * Note: we do not map DPTX PHY area, as that is handled by
+ * the PHY driver.
+ */
+ reg = <0x0 0xa000000 0x0 0x30a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
+ <0x0 0x4f40000 0x0 0x20>; /* DSS_EDP0_INTG_CFG_VP */
+ reg-names = "mhdptx", "j721e-intg";
+
+ clocks = <&k3_clks 151 36>;
+
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
+
+ power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
+
+ dp0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
dss: dss@4a00000 {
compatible = "ti,j721e-dss";
reg =
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v2 2/2] arm64: dts: ti: k3-j721e-common-proc-board: add DP to j7 evm
2022-03-31 14:30 [PATCH v2 0/2] DSS: Add support for DisplayPort Rahul T R
2022-03-31 14:30 ` [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: add DP & DP PHY Rahul T R
@ 2022-03-31 14:30 ` Rahul T R
2022-04-01 5:03 ` Vignesh Raghavendra
1 sibling, 1 reply; 5+ messages in thread
From: Rahul T R @ 2022-03-31 14:30 UTC (permalink / raw)
To: nm
Cc: vigneshr, kristo, robh+dt, krzysztof.kozlowski, linux-arm-kernel,
devicetree, linux-kernel, tomi.valkeinen, laurent.pinchart,
kishon, r-ravikumar
From: Tomi Valkeinen <tomi.valkeinen@ti.com>
Add the endpoint nodes to describe connection from
DSS => MHDP => DisplayPort connector.
Also add the phy link node and required pinmux nodes
for hotplug.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
---
.../dts/ti/k3-j721e-common-proc-board.dts | 78 ++++++++++++++++++-
1 file changed, 74 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index f5ca8e26ed99..8ddc0d3bd058 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -148,6 +148,28 @@
pinctrl-0 = <&main_mcan2_gpio_pins_default>;
standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>;
};
+
+ dp_pwr_3v3: fixedregulator-dp-prw {
+ compatible = "regulator-fixed";
+ regulator-name = "dp-pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&exp4 0 0>; /* P0 - DP0_PWR_SW_EN */
+ enable-active-high;
+ };
+
+ dp0: connector {
+ compatible = "dp-connector";
+ label = "DP0";
+ type = "full-size";
+ dp-pwr-supply = <&dp_pwr_3v3>;
+
+ port {
+ dp_connector_in: endpoint {
+ remote-endpoint = <&dp0_out>;
+ };
+ };
+ };
};
&main_pmx0 {
@@ -190,6 +212,12 @@
>;
};
+ dp0_pins_default: dp0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
+ >;
+ };
+
main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
pinctrl-single,pins = <
J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
@@ -658,6 +686,41 @@
<&k3_clks 152 18>; /* PLL23_HSDIV0 */
};
+&dss_ports {
+ port@0 {
+ reg = <0>;
+ dpi0_out: endpoint {
+ remote-endpoint = <&dp0_in>;
+ };
+ };
+};
+
+&mhdp {
+ phys = <&torrent_phy_dp>;
+ phy-names = "dpphy";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_pins_default>;
+};
+
+&dp0_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ dp0_out: endpoint {
+ remote-endpoint = <&dp_connector_in>;
+ };
+ };
+};
+
&mcasp0 {
status = "disabled";
};
@@ -793,6 +856,17 @@
};
};
+&serdes4 {
+ torrent_phy_dp: phy@0 {
+ reg = <0>;
+ resets = <&serdes_wiz4 1>;
+ cdns,phy-type = <PHY_TYPE_DP>;
+ cdns,num-lanes = <4>;
+ cdns,max-bit-rate = <5400>;
+ #phy-cells = <0>;
+ };
+};
+
&pcie0_rc {
reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
@@ -843,10 +917,6 @@
status = "disabled";
};
-&dss {
- status = "disabled";
-};
-
&icssg0_mdio {
status = "disabled";
};
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread