devicetree.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
	"Matthias Brugger" <matthias.bgg@gmail.com>,
	Will Deacon <will@kernel.org>
Cc: Robin Murphy <robin.murphy@arm.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	Tomasz Figa <tfiga@chromium.org>,
	<linux-mediatek@lists.infradead.org>,
	<srv_heupstream@mediatek.com>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<iommu@lists.linux-foundation.org>,
	Hsin-Yi Wang <hsinyi@chromium.org>, <yong.wu@mediatek.com>,
	<youlin.pei@mediatek.com>, <anan.sun@mediatek.com>,
	<xueqi.zhang@mediatek.com>, <yen-chang.chen@mediatek.com>,
	"AngeloGioacchino Del Regno" 
	<angelogioacchino.delregno@collabora.com>,
	<mingyuan.ma@mediatek.com>, <yf.wang@mediatek.com>,
	<libo.kang@mediatek.com>, <chengci.xu@mediatek.com>
Subject: [PATCH v6 02/34] dt-bindings: mediatek: mt8195: Add binding for infra IOMMU
Date: Thu, 7 Apr 2022 15:56:54 +0800	[thread overview]
Message-ID: <20220407075726.17771-3-yong.wu@mediatek.com> (raw)
In-Reply-To: <20220407075726.17771-1-yong.wu@mediatek.com>

In mt8195, we have a new IOMMU that is for INFRA IOMMU. its masters
mainly are PCIe and USB. Different with MM IOMMU, all these masters
connect with IOMMU directly, there is no mediatek,larbs property for
infra IOMMU.

Another thing is about PCIe ports. currently the function
"of_iommu_configure_dev_id" only support the id number is 1, But our
PCIe have two ports, one is for reading and the other is for writing.
see more about the PCIe patch in this patchset. Thus, I only list
the reading id here and add the other id in our driver.

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../bindings/iommu/mediatek,iommu.yaml         | 13 ++++++++++++-
 .../dt-bindings/memory/mt8195-memory-port.h    | 18 ++++++++++++++++++
 include/dt-bindings/memory/mtk-memory-port.h   |  2 ++
 3 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
index 2223408e91a9..eed59ec00e78 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -79,6 +79,7 @@ properties:
           - mediatek,mt8192-m4u  # generation two
           - mediatek,mt8195-iommu-vdo        # generation two
           - mediatek,mt8195-iommu-vpp        # generation two
+          - mediatek,mt8195-iommu-infra      # generation two
 
       - description: mt7623 generation one
         items:
@@ -131,7 +132,6 @@ required:
   - compatible
   - reg
   - interrupts
-  - mediatek,larbs
   - '#iommu-cells'
 
 allOf:
@@ -163,6 +163,17 @@ allOf:
       required:
         - power-domains
 
+  - if: # The IOMMUs don't have larbs.
+      not:
+        properties:
+          compatible:
+            contains:
+              const: mediatek,mt8195-iommu-infra
+
+    then:
+      required:
+        - mediatek,larbs
+
 additionalProperties: false
 
 examples:
diff --git a/include/dt-bindings/memory/mt8195-memory-port.h b/include/dt-bindings/memory/mt8195-memory-port.h
index c10e8b61f1e8..70ba9f498eeb 100644
--- a/include/dt-bindings/memory/mt8195-memory-port.h
+++ b/include/dt-bindings/memory/mt8195-memory-port.h
@@ -387,4 +387,22 @@
 #define M4U_PORT_L28_CAM_DRZS4NO_R1		MTK_M4U_ID(28, 5)
 #define M4U_PORT_L28_CAM_TNCSO_R1		MTK_M4U_ID(28, 6)
 
+/* Infra iommu ports */
+/* PCIe1: read: BIT16; write BIT17. */
+#define IOMMU_PORT_INFRA_PCIE1			MTK_IFAIOMMU_PERI_ID(16)
+/* PCIe0: read: BIT18; write BIT19. */
+#define IOMMU_PORT_INFRA_PCIE0			MTK_IFAIOMMU_PERI_ID(18)
+#define IOMMU_PORT_INFRA_SSUSB_P3_R		MTK_IFAIOMMU_PERI_ID(20)
+#define IOMMU_PORT_INFRA_SSUSB_P3_W		MTK_IFAIOMMU_PERI_ID(21)
+#define IOMMU_PORT_INFRA_SSUSB_P2_R		MTK_IFAIOMMU_PERI_ID(22)
+#define IOMMU_PORT_INFRA_SSUSB_P2_W		MTK_IFAIOMMU_PERI_ID(23)
+#define IOMMU_PORT_INFRA_SSUSB_P1_1_R		MTK_IFAIOMMU_PERI_ID(24)
+#define IOMMU_PORT_INFRA_SSUSB_P1_1_W		MTK_IFAIOMMU_PERI_ID(25)
+#define IOMMU_PORT_INFRA_SSUSB_P1_0_R		MTK_IFAIOMMU_PERI_ID(26)
+#define IOMMU_PORT_INFRA_SSUSB_P1_0_W		MTK_IFAIOMMU_PERI_ID(27)
+#define IOMMU_PORT_INFRA_SSUSB2_R		MTK_IFAIOMMU_PERI_ID(28)
+#define IOMMU_PORT_INFRA_SSUSB2_W		MTK_IFAIOMMU_PERI_ID(29)
+#define IOMMU_PORT_INFRA_SSUSB_R		MTK_IFAIOMMU_PERI_ID(30)
+#define IOMMU_PORT_INFRA_SSUSB_W		MTK_IFAIOMMU_PERI_ID(31)
+
 #endif
diff --git a/include/dt-bindings/memory/mtk-memory-port.h b/include/dt-bindings/memory/mtk-memory-port.h
index 7d64103209af..2f68a0511a25 100644
--- a/include/dt-bindings/memory/mtk-memory-port.h
+++ b/include/dt-bindings/memory/mtk-memory-port.h
@@ -12,4 +12,6 @@
 #define MTK_M4U_TO_LARB(id)		(((id) >> 5) & 0x1f)
 #define MTK_M4U_TO_PORT(id)		((id) & 0x1f)
 
+#define MTK_IFAIOMMU_PERI_ID(port)	MTK_M4U_ID(0, port)
+
 #endif
-- 
2.18.0


  parent reply	other threads:[~2022-04-07  7:58 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-07  7:56 [PATCH v6 00/34] MT8195 IOMMU SUPPORT Yong Wu
2022-04-07  7:56 ` [PATCH v6 01/34] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU Yong Wu
2022-04-07  7:56 ` Yong Wu [this message]
2022-04-07  7:56 ` [PATCH v6 03/34] iommu/mediatek: Fix 2 HW sharing pgtable issue Yong Wu
2022-04-07  7:56 ` [PATCH v6 04/34] iommu/mediatek: Add list_del in mtk_iommu_remove Yong Wu
2022-04-07  7:56 ` [PATCH v6 05/34] iommu/mediatek: Remove clk_disable " Yong Wu
2022-04-07  7:56 ` [PATCH v6 06/34] iommu/mediatek: Add mutex for m4u_group and m4u_dom in data Yong Wu
2022-04-07  7:56 ` [PATCH v6 07/34] iommu/mediatek: Add mutex for data in the mtk_iommu_domain Yong Wu
2022-04-07  7:57 ` [PATCH v6 08/34] iommu/mediatek: Adapt sharing and non-sharing pgtable case Yong Wu
2022-04-07  7:57 ` [PATCH v6 09/34] iommu/mediatek: Add 12G~16G support for multi domains Yong Wu
2022-04-07  7:57 ` [PATCH v6 10/34] iommu/mediatek: Add a flag DCM_DISABLE Yong Wu
2022-04-07  7:57 ` [PATCH v6 11/34] iommu/mediatek: Add a flag NON_STD_AXI Yong Wu
2022-04-28 14:52   ` Matthias Brugger
2022-04-07  7:57 ` [PATCH v6 12/34] iommu/mediatek: Remove the granule in the tlb flush Yong Wu
2022-04-07  7:57 ` [PATCH v6 13/34] iommu/mediatek: Always enable output PA over 32bits in isr Yong Wu
2022-04-07  7:57 ` [PATCH v6 14/34] iommu/mediatek: Add SUB_COMMON_3BITS flag Yong Wu
2022-04-07  7:57 ` [PATCH v6 15/34] iommu/mediatek: Add IOMMU_TYPE flag Yong Wu
2022-04-28 14:17   ` Matthias Brugger
2022-04-07  7:57 ` [PATCH v6 16/34] iommu/mediatek: Contain MM IOMMU flow with the MM TYPE Yong Wu
2022-04-07  7:57 ` [PATCH v6 17/34] iommu/mediatek: Adjust device link when it is sub-common Yong Wu
2022-04-07  7:57 ` [PATCH v6 18/34] iommu/mediatek: Allow IOMMU_DOMAIN_UNMANAGED for PCIe VFIO Yong Wu
2022-04-07  7:57 ` [PATCH v6 19/34] iommu/mediatek: Add a PM_CLK_AO flag for infra iommu Yong Wu
2022-04-07  7:57 ` [PATCH v6 20/34] iommu/mediatek: Add infra iommu support Yong Wu
2022-04-07  7:57 ` [PATCH v6 21/34] iommu/mediatek: Add PCIe support Yong Wu
2022-04-07  7:57 ` [PATCH v6 22/34] iommu/mediatek: Add mt8195 support Yong Wu
2022-04-07  7:57 ` [PATCH v6 23/34] iommu/mediatek: Only adjust code about register base Yong Wu
2022-04-07  7:57 ` [PATCH v6 24/34] iommu/mediatek: Just move code position in hw_init Yong Wu
2022-04-07  7:57 ` [PATCH v6 25/34] iommu/mediatek: Separate mtk_iommu_data for v1 and v2 Yong Wu
2022-04-07  7:57 ` [PATCH v6 26/34] iommu/mediatek: Remove mtk_iommu.h Yong Wu
2022-04-07  7:57 ` [PATCH v6 27/34] iommu/mediatek-v1: Just rename mtk_iommu to mtk_iommu_v1 Yong Wu
2022-04-07  7:57 ` [PATCH v6 28/34] iommu/mediatek: Add mtk_iommu_bank_data structure Yong Wu
2022-04-07  7:57 ` [PATCH v6 29/34] iommu/mediatek: Initialise bank HW for each a bank Yong Wu
2022-04-07  7:57 ` [PATCH v6 30/34] iommu/mediatek: Change the domid to iova_region_id Yong Wu
2022-04-07  7:57 ` [PATCH v6 31/34] iommu/mediatek: Get the proper bankid for multi banks Yong Wu
2022-04-28 14:14   ` Matthias Brugger
2022-05-01  2:33     ` Yong Wu
2022-04-07  7:57 ` [PATCH v6 32/34] iommu/mediatek: Initialise/Remove for multi bank dev Yong Wu
2022-04-07  7:57 ` [PATCH v6 33/34] iommu/mediatek: Backup/restore regsiters for multi banks Yong Wu
2022-04-07  7:57 ` [PATCH v6 34/34] iommu/mediatek: mt8195: Enable multi banks for infra iommu Yong Wu
2022-04-19  9:00 ` [PATCH v6 00/34] MT8195 IOMMU SUPPORT AngeloGioacchino Del Regno

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220407075726.17771-3-yong.wu@mediatek.com \
    --to=yong.wu@mediatek.com \
    --cc=anan.sun@mediatek.com \
    --cc=angelogioacchino.delregno@collabora.com \
    --cc=chengci.xu@mediatek.com \
    --cc=devicetree@vger.kernel.org \
    --cc=hsinyi@chromium.org \
    --cc=iommu@lists.linux-foundation.org \
    --cc=joro@8bytes.org \
    --cc=krzysztof.kozlowski@canonical.com \
    --cc=libo.kang@mediatek.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mediatek@lists.infradead.org \
    --cc=matthias.bgg@gmail.com \
    --cc=mingyuan.ma@mediatek.com \
    --cc=robh+dt@kernel.org \
    --cc=robin.murphy@arm.com \
    --cc=srv_heupstream@mediatek.com \
    --cc=tfiga@chromium.org \
    --cc=will@kernel.org \
    --cc=xueqi.zhang@mediatek.com \
    --cc=yen-chang.chen@mediatek.com \
    --cc=yf.wang@mediatek.com \
    --cc=youlin.pei@mediatek.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).