From: Conor Dooley <conor.dooley@microchip.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<aou@eecs.berkeley.edu>, <paul.walmsley@sifive.com>,
<palmer@rivosinc.com>, <a.zummo@towertech.it>,
<alexandre.belloni@bootlin.com>, <robh+dt@kernel.org>,
<krzk+dt@kernel.org>
Cc: <daire.mcnamara@microchip.com>, <linux-rtc@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<linux-riscv@lists.infradead.org>,
Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v1 3/7] dt-bindings: rtc: add refclk to mpfs-rtc
Date: Fri, 8 Apr 2022 14:36:43 +0000 [thread overview]
Message-ID: <20220408143646.3693104-4-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220408143646.3693104-1-conor.dooley@microchip.com>
The rtc on PolarFire SoC does not use the AHB clock as its reference
frequency, but rather a 1 MHz refclk that it shares with MTIMER. Add
this second clock to the binding as a required property.
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/rtc/microchip,mfps-rtc.yaml | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
index a2e984ea3553..1ffd97dbe6b9 100644
--- a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
+++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
@@ -31,11 +31,18 @@ properties:
to that of the RTC's count register.
clocks:
- maxItems: 1
+ items:
+ - description: |
+ AHB clock
+ - description: |
+ Reference clock: divided by the prescaler to create a time-based strobe (typically 1 Hz)
+ for the calendar counter. By default, the rtc on the PolarFire SoC shares it's reference
+ with MTIMER so this will be a 1 MHz clock.
clock-names:
items:
- const: rtc
+ - const: rtcref
required:
- compatible
@@ -48,11 +55,12 @@ additionalProperties: false
examples:
- |
+ #include "dt-bindings/clock/microchip,mpfs-clock.h"
rtc@20124000 {
compatible = "microchip,mpfs-rtc";
reg = <0x20124000 0x1000>;
- clocks = <&clkcfg 21>;
- clock-names = "rtc";
+ clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
+ clock-names = "rtc", "rtcref";
interrupts = <80>, <81>;
};
...
--
2.35.1
next prev parent reply other threads:[~2022-04-08 14:37 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-08 14:36 [PATCH v1 0/7] Add rtc refclk support for PolarFire SoC Conor Dooley
2022-04-08 14:36 ` [PATCH v1 1/7] dt-bindings: clk: mpfs document msspll dri registers Conor Dooley
2022-04-08 14:54 ` Krzysztof Kozlowski
2022-04-08 14:36 ` [PATCH v1 2/7] dt-bindings: clk: mpfs: add defines for two new clocks Conor Dooley
2022-04-08 14:36 ` Conor Dooley [this message]
2022-04-08 14:56 ` [PATCH v1 3/7] dt-bindings: rtc: add refclk to mpfs-rtc Krzysztof Kozlowski
2022-04-08 14:36 ` [PATCH v1 4/7] clk: microchip: mpfs: re-parent the configurable clocks Conor Dooley
2022-04-08 14:36 ` [PATCH v1 5/7] clk: microchip: mpfs: rename sys_base to base Conor Dooley
2022-04-08 14:36 ` [PATCH v1 6/7] clk: microchip: mpfs: add RTCREF clock control Conor Dooley
2022-04-08 14:36 ` [PATCH v1 7/7] riscv: dts: microchip: reparent mpfs clocks Conor Dooley
2022-04-08 14:57 ` [PATCH v1 0/7] Add rtc refclk support for PolarFire SoC Krzysztof Kozlowski
2022-04-08 15:29 ` Conor Dooley
2022-04-09 7:14 ` Conor Dooley
2022-04-09 10:48 ` Krzysztof Kozlowski
2022-04-09 20:17 ` Conor Dooley
2022-04-10 8:12 ` Krzysztof Kozlowski
2022-04-09 10:45 ` Krzysztof Kozlowski
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