From: Conor Dooley <conor.dooley@microchip.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<aou@eecs.berkeley.edu>, <paul.walmsley@sifive.com>,
<palmer@rivosinc.com>, <a.zummo@towertech.it>,
<alexandre.belloni@bootlin.com>, <robh+dt@kernel.org>,
<krzk+dt@kernel.org>
Cc: <daire.mcnamara@microchip.com>, <linux-rtc@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<linux-riscv@lists.infradead.org>,
Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v1 5/7] clk: microchip: mpfs: rename sys_base to base
Date: Fri, 8 Apr 2022 14:36:45 +0000 [thread overview]
Message-ID: <20220408143646.3693104-6-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220408143646.3693104-1-conor.dooley@microchip.com>
Having added a second set of registers for the msspll, sys_base no longer
really makes sense as a variable name. Renaming it to base will make it
consistent with mpfs_clock_data & several function arguments.
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
drivers/clk/microchip/clk-mpfs.c | 30 +++++++++++++++---------------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c
index 66251a5f4a03..f22d4b40ef28 100644
--- a/drivers/clk/microchip/clk-mpfs.c
+++ b/drivers/clk/microchip/clk-mpfs.c
@@ -55,7 +55,7 @@ struct mpfs_cfg_clock {
struct mpfs_cfg_hw_clock {
struct mpfs_cfg_clock cfg;
- void __iomem *sys_base;
+ void __iomem *base;
struct clk_hw hw;
struct clk_init_data init;
};
@@ -69,7 +69,7 @@ struct mpfs_periph_clock {
struct mpfs_periph_hw_clock {
struct mpfs_periph_clock periph;
- void __iomem *sys_base;
+ void __iomem *base;
struct clk_hw hw;
};
@@ -168,7 +168,7 @@ static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long p
{
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
- void __iomem *base_addr = cfg_hw->sys_base;
+ void __iomem *base_addr = cfg_hw->base;
u32 val;
val = readl_relaxed(base_addr + cfg->reg_offset) >> cfg->shift;
@@ -189,7 +189,7 @@ static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned
{
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
- void __iomem *base_addr = cfg_hw->sys_base;
+ void __iomem *base_addr = cfg_hw->base;
unsigned long flags;
u32 val;
int divider_setting;
@@ -236,9 +236,9 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
};
static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw,
- void __iomem *sys_base)
+ void __iomem *base)
{
- cfg_hw->sys_base = sys_base;
+ cfg_hw->base = base;
return devm_clk_hw_register(dev, &cfg_hw->hw);
}
@@ -246,14 +246,14 @@ static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *c
static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws,
unsigned int num_clks, struct mpfs_clock_data *data)
{
- void __iomem *sys_base = data->base;
+ void __iomem *base = data->base;
unsigned int i, id;
int ret;
for (i = 0; i < num_clks; i++) {
struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i];
- ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base);
+ ret = mpfs_clk_register_cfg(dev, cfg_hw, base);
if (ret)
return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
cfg_hw->cfg.id);
@@ -273,7 +273,7 @@ static int mpfs_periph_clk_enable(struct clk_hw *hw)
{
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
struct mpfs_periph_clock *periph = &periph_hw->periph;
- void __iomem *base_addr = periph_hw->sys_base;
+ void __iomem *base_addr = periph_hw->base;
u32 reg, val;
unsigned long flags;
@@ -292,7 +292,7 @@ static void mpfs_periph_clk_disable(struct clk_hw *hw)
{
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
struct mpfs_periph_clock *periph = &periph_hw->periph;
- void __iomem *base_addr = periph_hw->sys_base;
+ void __iomem *base_addr = periph_hw->base;
u32 reg, val;
unsigned long flags;
@@ -309,7 +309,7 @@ static int mpfs_periph_clk_is_enabled(struct clk_hw *hw)
{
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
struct mpfs_periph_clock *periph = &periph_hw->periph;
- void __iomem *base_addr = periph_hw->sys_base;
+ void __iomem *base_addr = periph_hw->base;
u32 reg;
reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR);
@@ -379,9 +379,9 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
};
static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw,
- void __iomem *sys_base)
+ void __iomem *base)
{
- periph_hw->sys_base = sys_base;
+ periph_hw->base = base;
return devm_clk_hw_register(dev, &periph_hw->hw);
}
@@ -389,14 +389,14 @@ static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_cl
static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws,
int num_clks, struct mpfs_clock_data *data)
{
- void __iomem *sys_base = data->base;
+ void __iomem *base = data->base;
unsigned int i, id;
int ret;
for (i = 0; i < num_clks; i++) {
struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i];
- ret = mpfs_clk_register_periph(dev, periph_hw, sys_base);
+ ret = mpfs_clk_register_periph(dev, periph_hw, base);
if (ret)
return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
periph_hw->periph.id);
--
2.35.1
next prev parent reply other threads:[~2022-04-08 14:38 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-08 14:36 [PATCH v1 0/7] Add rtc refclk support for PolarFire SoC Conor Dooley
2022-04-08 14:36 ` [PATCH v1 1/7] dt-bindings: clk: mpfs document msspll dri registers Conor Dooley
2022-04-08 14:54 ` Krzysztof Kozlowski
2022-04-08 14:36 ` [PATCH v1 2/7] dt-bindings: clk: mpfs: add defines for two new clocks Conor Dooley
2022-04-08 14:36 ` [PATCH v1 3/7] dt-bindings: rtc: add refclk to mpfs-rtc Conor Dooley
2022-04-08 14:56 ` Krzysztof Kozlowski
2022-04-08 14:36 ` [PATCH v1 4/7] clk: microchip: mpfs: re-parent the configurable clocks Conor Dooley
2022-04-08 14:36 ` Conor Dooley [this message]
2022-04-08 14:36 ` [PATCH v1 6/7] clk: microchip: mpfs: add RTCREF clock control Conor Dooley
2022-04-08 14:36 ` [PATCH v1 7/7] riscv: dts: microchip: reparent mpfs clocks Conor Dooley
2022-04-08 14:57 ` [PATCH v1 0/7] Add rtc refclk support for PolarFire SoC Krzysztof Kozlowski
2022-04-08 15:29 ` Conor Dooley
2022-04-09 7:14 ` Conor Dooley
2022-04-09 10:48 ` Krzysztof Kozlowski
2022-04-09 20:17 ` Conor Dooley
2022-04-10 8:12 ` Krzysztof Kozlowski
2022-04-09 10:45 ` Krzysztof Kozlowski
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