From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D28B4C433EF for ; Mon, 11 Apr 2022 07:32:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245493AbiDKHfK (ORCPT ); Mon, 11 Apr 2022 03:35:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243846AbiDKHfK (ORCPT ); Mon, 11 Apr 2022 03:35:10 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 945743D4A9 for ; Mon, 11 Apr 2022 00:32:56 -0700 (PDT) Received: by mail-pj1-x102c.google.com with SMTP id mp16-20020a17090b191000b001cb5efbcab6so5311651pjb.4 for ; Mon, 11 Apr 2022 00:32:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=6Bcipwo2t195QVJFmmzu71Z0FtdQvx0x9uvTartKReE=; b=xz0kRGucxrAsw2ENDOBT3/CQ9WGjLIBdTL9q2ce5qSASw2pV2bZWB6F+yDGWkvLf1D YxnUb9YnUe3wn7BgQ0ZOs6vfP+ItQdzWbEoFt2nTmyjOi2f5EZx9rJGN94j/ZDnW7zVd 9pnif/5B0u6JiEal2wcP7UwObcgwinWIvVCjS9xDCU0TV3lbs4LLNddQQPgUsQ4DzFfP pXpo0E+nIsC1ZyDewoFR8lVwiGCmGW2zOLmOlaoBMv9TUMGGNHOSBr05gOSU3EeECvDB MhJhcKTUGBmoQ0gCOWPkr7M4ZJsmq22zEZ+6KKcDnYoASH4qjp2Te1RbUmyPjBq4PcF5 Rx8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=6Bcipwo2t195QVJFmmzu71Z0FtdQvx0x9uvTartKReE=; b=LCbgx55Bcgb8IVhczMdoaoUva+AJAWIGKl5NyAhsC4kde+7vXbeI5Hh28Tx1gelYTR 4gi9WwULp65AO8ag5JrgWDo3F1bNp4hg1dVLvUk60dffQRR97N458j13cktCh2+CQ6qz cLX7Tt+zPGs49ofFMGVQ45nBm9L/5TzlZcZMZbjbUYEU+Z4JuYRuJHyVCLZMBFSFHh2A GfEILp3KmEXHBsgXIgYKez/hW5G6ja0urVLE6d4voLXIMYhUT6fQPnKFC5orcPhtxh/d Cs/G3syxc2huMtnnqTTw1vMAQhXl6tHI/mbKGZZTWPnd28mn75g+IqiIrgkPa1d54mOj C5Dw== X-Gm-Message-State: AOAM530O6cuSPdWK6zd4edKarW28IdnBUqS6o1qjLSPftZO7q+b/9Cla WZKZRaNZNim7YGcBUoBIOwlu X-Google-Smtp-Source: ABdhPJymDSL0wYm7Gy/Y8s9Ov9nZtnJdrl315iiyAsoeZ3s3YHNZuGUWiSY5ZkcV20aurQGIxbOq8A== X-Received: by 2002:a17:90b:4b0e:b0:1c6:f499:1cc9 with SMTP id lx14-20020a17090b4b0e00b001c6f4991cc9mr35475405pjb.133.1649662376064; Mon, 11 Apr 2022 00:32:56 -0700 (PDT) Received: from thinkpad ([117.217.182.106]) by smtp.gmail.com with ESMTPSA id x6-20020a056a000bc600b005058a09f3aesm10186371pfu.147.2022.04.11.00.32.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 00:32:55 -0700 (PDT) Date: Mon, 11 Apr 2022 13:02:46 +0530 From: Manivannan Sadhasivam To: Rohit Agarwal Cc: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH 5/7] ARM: dts: qcom: sdx65: Enable ARM SMMU Message-ID: <20220411073246.GD24975@thinkpad> References: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> <1649660143-22400-6-git-send-email-quic_rohiagar@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1649660143-22400-6-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Apr 11, 2022 at 12:25:41PM +0530, Rohit Agarwal wrote: > Add a node for the ARM SMMU found in the SDX65. > > Signed-off-by: Rohit Agarwal > --- > arch/arm/boot/dts/qcom-sdx65.dtsi | 40 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi > index 632ac78..2481769 100644 > --- a/arch/arm/boot/dts/qcom-sdx65.dtsi > +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi > @@ -181,6 +181,46 @@ > status = "disabled"; > }; > > + apps_smmu: iommu@15000000 { Please sort the nodes in ascending order. Thanks, Mani > + compatible = "qcom,sdx65-smmu-500", "arm,mmu-500"; > + reg = <0x15000000 0x40000>; > + #iommu-cells = <2>; > + #global-interrupts = <1>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + }; > + > pdc: interrupt-controller@b210000 { > compatible = "qcom,sdx65-pdc", "qcom,pdc"; > reg = <0xb210000 0x10000>; > -- > 2.7.4 >