* [PATCH 0/2] Add support for USB3 PHY on SDX65
@ 2022-04-12 5:17 Rohit Agarwal
2022-04-12 5:17 ` [PATCH 1/2] dt-bindings: phy: qcom,qmp: Add SDX65 USB PHY binding Rohit Agarwal
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Rohit Agarwal @ 2022-04-12 5:17 UTC (permalink / raw)
To: agross, bjorn.andersson, kishon, vkoul, robh+dt, krzk+dt
Cc: manivannan.sadhasivam, linux-arm-msm, linux-phy, devicetree,
linux-kernel, Rohit Agarwal
This series adds USB3 PHY support for SDX65 platform. The USB3 PHY is of
type QMP and revision 5.0.0.
Thanks,
Rohit.
Rohit Agarwal (2):
dt-bindings: phy: qcom,qmp: Add SDX65 USB PHY binding
phy: qcom-qmp: Add support for SDX65 QMP PHY
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 +
drivers/phy/qualcomm/phy-qcom-qmp.c | 76 ++++++++++++++++++++++
2 files changed, 78 insertions(+)
--
2.7.4
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 1/2] dt-bindings: phy: qcom,qmp: Add SDX65 USB PHY binding 2022-04-12 5:17 [PATCH 0/2] Add support for USB3 PHY on SDX65 Rohit Agarwal @ 2022-04-12 5:17 ` Rohit Agarwal 2022-04-12 9:21 ` Krzysztof Kozlowski 2022-04-12 5:17 ` [PATCH 2/2] phy: qcom-qmp: Add support for SDX65 QMP PHY Rohit Agarwal 2022-04-13 7:55 ` [PATCH 0/2] Add support for USB3 PHY on SDX65 Vinod Koul 2 siblings, 1 reply; 6+ messages in thread From: Rohit Agarwal @ 2022-04-12 5:17 UTC (permalink / raw) To: agross, bjorn.andersson, kishon, vkoul, robh+dt, krzk+dt Cc: manivannan.sadhasivam, linux-arm-msm, linux-phy, devicetree, linux-kernel, Rohit Agarwal Add devicetree YAML binding for Qualcomm QMP Super Speed (SS) PHY found in SDX65. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index e417cd6..57273f1 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -56,6 +56,7 @@ properties: - qcom,sm8450-qmp-usb3-phy - qcom,sdx55-qmp-pcie-phy - qcom,sdx55-qmp-usb3-uni-phy + - qcom,sdx65-qmp-usb3-uni-phy reg: minItems: 1 @@ -162,6 +163,7 @@ allOf: contains: enum: - qcom,sdx55-qmp-usb3-uni-phy + - qcom,sdx65-qmp-usb3-uni-phy then: properties: clocks: -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] dt-bindings: phy: qcom,qmp: Add SDX65 USB PHY binding 2022-04-12 5:17 ` [PATCH 1/2] dt-bindings: phy: qcom,qmp: Add SDX65 USB PHY binding Rohit Agarwal @ 2022-04-12 9:21 ` Krzysztof Kozlowski 0 siblings, 0 replies; 6+ messages in thread From: Krzysztof Kozlowski @ 2022-04-12 9:21 UTC (permalink / raw) To: Rohit Agarwal, agross, bjorn.andersson, kishon, vkoul, robh+dt, krzk+dt Cc: manivannan.sadhasivam, linux-arm-msm, linux-phy, devicetree, linux-kernel On 12/04/2022 07:17, Rohit Agarwal wrote: > Add devicetree YAML binding for Qualcomm QMP Super Speed (SS) PHY found > in SDX65. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] phy: qcom-qmp: Add support for SDX65 QMP PHY 2022-04-12 5:17 [PATCH 0/2] Add support for USB3 PHY on SDX65 Rohit Agarwal 2022-04-12 5:17 ` [PATCH 1/2] dt-bindings: phy: qcom,qmp: Add SDX65 USB PHY binding Rohit Agarwal @ 2022-04-12 5:17 ` Rohit Agarwal 2022-04-13 7:34 ` Manivannan Sadhasivam 2022-04-13 7:55 ` [PATCH 0/2] Add support for USB3 PHY on SDX65 Vinod Koul 2 siblings, 1 reply; 6+ messages in thread From: Rohit Agarwal @ 2022-04-12 5:17 UTC (permalink / raw) To: agross, bjorn.andersson, kishon, vkoul, robh+dt, krzk+dt Cc: manivannan.sadhasivam, linux-arm-msm, linux-phy, devicetree, linux-kernel, Rohit Agarwal Add support for USB3 QMP PHY found in SDX65 platform. SDX65 uses version 5.0.0 of the QMP PHY IP. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> --- drivers/phy/qualcomm/phy-qcom-qmp.c | 76 +++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 8ea87c6..58506b8 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -2535,6 +2535,50 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), }; +static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b), +}; + +static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), +}; + static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), @@ -4217,6 +4261,35 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .pwrdn_delay_max = 1005, /* us */ }; +static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, + + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), + .tx_tbl = sdx65_usb3_uniphy_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl), + .rx_tbl = sdx65_usb3_uniphy_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl), + .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), + .clk_list = qmp_v4_sdx55_usbphy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8350_usb3_uniphy_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +}; + static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { .type = PHY_TYPE_UFS, .nlanes = 2, @@ -6044,6 +6117,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { .compatible = "qcom,sdx55-qmp-usb3-uni-phy", .data = &sdx55_usb3_uniphy_cfg, }, { + .compatible = "qcom,sdx65-qmp-usb3-uni-phy", + .data = &sdx65_usb3_uniphy_cfg, + }, { .compatible = "qcom,sm8350-qmp-usb3-phy", .data = &sm8350_usb3phy_cfg, }, { -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] phy: qcom-qmp: Add support for SDX65 QMP PHY 2022-04-12 5:17 ` [PATCH 2/2] phy: qcom-qmp: Add support for SDX65 QMP PHY Rohit Agarwal @ 2022-04-13 7:34 ` Manivannan Sadhasivam 0 siblings, 0 replies; 6+ messages in thread From: Manivannan Sadhasivam @ 2022-04-13 7:34 UTC (permalink / raw) To: Rohit Agarwal Cc: agross, bjorn.andersson, kishon, vkoul, robh+dt, krzk+dt, linux-arm-msm, linux-phy, devicetree, linux-kernel On Tue, Apr 12, 2022 at 10:47:32AM +0530, Rohit Agarwal wrote: > Add support for USB3 QMP PHY found in SDX65 platform. SDX65 uses > version 5.0.0 of the QMP PHY IP. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> I don't have access to SDX65 downstream devicetree source but overall it looks good to me. Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Thanks, Mani > --- > drivers/phy/qualcomm/phy-qcom-qmp.c | 76 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 76 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c > index 8ea87c6..58506b8 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c > @@ -2535,6 +2535,50 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { > QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), > }; > > +static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { > + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), > + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), > + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), > + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), > + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), > + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), > + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b), > +}; > + > +static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), > +}; > + > static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { > QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), > QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), > @@ -4217,6 +4261,35 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { > .pwrdn_delay_max = 1005, /* us */ > }; > > +static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { > + .type = PHY_TYPE_USB3, > + .nlanes = 1, > + > + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, > + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), > + .tx_tbl = sdx65_usb3_uniphy_tx_tbl, > + .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl), > + .rx_tbl = sdx65_usb3_uniphy_rx_tbl, > + .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl), > + .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, > + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), > + .clk_list = qmp_v4_sdx55_usbphy_clk_l, > + .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), > + .reset_list = msm8996_usb3phy_reset_l, > + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), > + .vreg_list = qmp_phy_vreg_l, > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), > + .regs = sm8350_usb3_uniphy_regs_layout, > + > + .start_ctrl = SERDES_START | PCS_START, > + .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS, > + > + .has_pwrdn_delay = true, > + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, > + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, > +}; > + > static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { > .type = PHY_TYPE_UFS, > .nlanes = 2, > @@ -6044,6 +6117,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { > .compatible = "qcom,sdx55-qmp-usb3-uni-phy", > .data = &sdx55_usb3_uniphy_cfg, > }, { > + .compatible = "qcom,sdx65-qmp-usb3-uni-phy", > + .data = &sdx65_usb3_uniphy_cfg, > + }, { > .compatible = "qcom,sm8350-qmp-usb3-phy", > .data = &sm8350_usb3phy_cfg, > }, { > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/2] Add support for USB3 PHY on SDX65 2022-04-12 5:17 [PATCH 0/2] Add support for USB3 PHY on SDX65 Rohit Agarwal 2022-04-12 5:17 ` [PATCH 1/2] dt-bindings: phy: qcom,qmp: Add SDX65 USB PHY binding Rohit Agarwal 2022-04-12 5:17 ` [PATCH 2/2] phy: qcom-qmp: Add support for SDX65 QMP PHY Rohit Agarwal @ 2022-04-13 7:55 ` Vinod Koul 2 siblings, 0 replies; 6+ messages in thread From: Vinod Koul @ 2022-04-13 7:55 UTC (permalink / raw) To: Rohit Agarwal Cc: agross, bjorn.andersson, kishon, robh+dt, krzk+dt, manivannan.sadhasivam, linux-arm-msm, linux-phy, devicetree, linux-kernel On 12-04-22, 10:47, Rohit Agarwal wrote: > This series adds USB3 PHY support for SDX65 platform. The USB3 PHY is of > type QMP and revision 5.0.0. Applied, thanks -- ~Vinod ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-04-13 7:55 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-04-12 5:17 [PATCH 0/2] Add support for USB3 PHY on SDX65 Rohit Agarwal 2022-04-12 5:17 ` [PATCH 1/2] dt-bindings: phy: qcom,qmp: Add SDX65 USB PHY binding Rohit Agarwal 2022-04-12 9:21 ` Krzysztof Kozlowski 2022-04-12 5:17 ` [PATCH 2/2] phy: qcom-qmp: Add support for SDX65 QMP PHY Rohit Agarwal 2022-04-13 7:34 ` Manivannan Sadhasivam 2022-04-13 7:55 ` [PATCH 0/2] Add support for USB3 PHY on SDX65 Vinod Koul
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