From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EC2DC433FE for ; Wed, 13 Apr 2022 08:02:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233659AbiDMIEc (ORCPT ); Wed, 13 Apr 2022 04:04:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232839AbiDMIEb (ORCPT ); Wed, 13 Apr 2022 04:04:31 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 676C32A706; Wed, 13 Apr 2022 01:02:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649836931; x=1681372931; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=F5JKJ+sKckh/Yv3PJH0Wx7ATRoah+9bM8XitYjEZqzE=; b=CuWz/r8ia70rQvuM8lFGW5r6n8RcUiChopZnTlPtVHDmAWMAVvoxC3J3 jS1k37Klg/M/S3lnIZ9kz2ova/LaIMYXER8Ky2qd9W3PnsRAb3v5KFocy eyI5gOstaYxg1+nhz0Wr/vXO2jZBR4OM+c1Cd3q4rY7h7phLm1u49LjQO /+YSn8o8oqtftvTgpA0VZ7t/BJaoV4HWNYAbETrA654YLjGM9vAPzgs82 B4MchYUHPrSBHJsBp6IYqJ1TsLsDlyr33EmnY02iivu2axZQuXuPWaaUE dHWvMDnmIibaOWaC77dc6ynsqaNv6pouBvNt7ceSJmfdWC10iibNwLIPG Q==; X-IronPort-AV: E=Sophos;i="5.90,256,1643698800"; d="scan'208";a="159940058" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Apr 2022 01:02:11 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 13 Apr 2022 01:02:10 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 13 Apr 2022 01:02:07 -0700 From: Conor Dooley To: , , , , , , , , CC: , , , , , Conor Dooley , Krzysztof Kozlowski Subject: [PATCH v3 4/9] dt-bindings: clk: mpfs document msspll dri registers Date: Wed, 13 Apr 2022 08:58:31 +0100 Message-ID: <20220413075835.3354193-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220413075835.3354193-1-conor.dooley@microchip.com> References: <20220413075835.3354193-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As there are two sections of registers that are responsible for clock configuration on the PolarFire SoC: add the dynamic reconfiguration interface section to the binding & describe what each of the sections are used for. Fixes: 2145bb687e3f ("dt-bindings: clk: microchip: Add Microchip PolarFire host binding") Reviewed-by: Daire McNamara Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- .../devicetree/bindings/clock/microchip,mpfs.yaml | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml index 0c15afa2214c..016a4f378b9b 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml @@ -22,7 +22,16 @@ properties: const: microchip,mpfs-clkcfg reg: - maxItems: 1 + items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for the, cpu, + axi, ahb and rtc/mtimer reference clocks as well as enable and reset + for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration of the mss + pll clocks: maxItems: 1 @@ -51,7 +60,7 @@ examples: #size-cells = <2>; clkcfg: clock-controller@20002000 { compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>; + reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; clocks = <&ref>; #clock-cells = <1>; }; -- 2.35.1