From: Michael Walle <michael@walle.cc>
To: Alexandre Belloni <alexandre.belloni@bootlin.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: UNGLinuxDriver@microchip.com, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Michael Walle <michael@walle.cc>
Subject: [PATCH 2/3] MIPS: mscc: ocelot: rename pinctrl nodes
Date: Wed, 20 Apr 2022 21:50:17 +0200 [thread overview]
Message-ID: <20220420195018.3417053-2-michael@walle.cc> (raw)
In-Reply-To: <20220420195018.3417053-1-michael@walle.cc>
The pinctrl device tree binding will be converted to YAML format. Rename
the pin nodes so they end with "-pins" to match the schema.
Signed-off-by: Michael Walle <michael@walle.cc>
---
The YAML conversion patch is alread in
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=devel
arch/mips/boot/dts/mscc/ocelot.dtsi | 4 ++--
arch/mips/boot/dts/mscc/ocelot_pcb120.dts | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
index e51db651af13..cfc219a72bdd 100644
--- a/arch/mips/boot/dts/mscc/ocelot.dtsi
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -225,7 +225,7 @@ uart2_pins: uart2-pins {
function = "uart2";
};
- miim1: miim1 {
+ miim1_pins: miim1-pins {
pins = "GPIO_14", "GPIO_15";
function = "miim";
};
@@ -261,7 +261,7 @@ mdio1: mdio@10700c0 {
reg = <0x10700c0 0x24>;
interrupts = <15>;
pinctrl-names = "default";
- pinctrl-0 = <&miim1>;
+ pinctrl-0 = <&miim1_pins>;
status = "disabled";
};
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
index bd240690cb37..d348742c233d 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
@@ -22,12 +22,12 @@ memory@0 {
};
&gpio {
- phy_int_pins: phy_int_pins {
+ phy_int_pins: phy-int-pins {
pins = "GPIO_4";
function = "gpio";
};
- phy_load_save_pins: phy_load_save_pins {
+ phy_load_save_pins: phy-load-save-pins {
pins = "GPIO_10";
function = "ptp2";
};
@@ -40,7 +40,7 @@ &mdio0 {
&mdio1 {
status = "okay";
pinctrl-names = "default";
- pinctrl-0 = <&miim1>, <&phy_int_pins>, <&phy_load_save_pins>;
+ pinctrl-0 = <&miim1_pins>, <&phy_int_pins>, <&phy_load_save_pins>;
phy7: ethernet-phy@0 {
reg = <0>;
--
2.30.2
next prev parent reply other threads:[~2022-04-20 19:50 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-20 19:50 [PATCH 1/3] MIPS: mscc: jaguar2: rename pinctrl nodes Michael Walle
2022-04-20 19:50 ` Michael Walle [this message]
2022-04-20 19:50 ` [PATCH 3/3] MIPS: mscc: serval: " Michael Walle
2022-04-27 9:00 ` [PATCH 1/3] MIPS: mscc: jaguar2: " Thomas Bogendoerfer
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