From: Rex-BC Chen <rex-bc.chen@mediatek.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<matthias.bgg@gmail.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>
Cc: <p.zabel@pengutronix.de>,
<angelogioacchino.delregno@collabora.com>,
<chun-jie.chen@mediatek.com>, <wenst@chromium.org>,
<runyang.chen@mediatek.com>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Rex-BC Chen <rex-bc.chen@mediatek.com>
Subject: [PATCH V3 00/17] Cleanup MediaTek clk reset drivers and support MT8192/MT8195
Date: Fri, 22 Apr 2022 14:01:35 +0800 [thread overview]
Message-ID: <20220422060152.13534-1-rex-bc.chen@mediatek.com> (raw)
In this series, we cleanup MediaTek clock reset drivers in clk/mediatek
folder. MediaTek clock reset driver is used to provide reset control
of modules controlled in clk, like infra_ao.
Changes for V3:
1. Modify drivers for reviewers' comments.
2. Add dt-binding patch for MT8192/MT8195 infra.
3. Add reset property of infra node for MT8192.
4. Use original function for simple operation.
Changes for V2:
1. Modify drivers for reviewers' comments.
2. Use simple reset to replace v1.
3. Recover v2 to set_clr.
4. Separate error handling to another patch.
5. Add support for input offset and bit from DT.
6. Add support for MT8192 and MT8195.
Rex-BC Chen (17):
clk: mediatek: reset: Add reset.h
clk: mediatek: reset: Fix written reset bit offset
clk: mediatek: reset: Refine and reorder functions in reset.c
clk: mediatek: reset: Extract common drivers to update function
clk: mediatek: reset: Merge and revise reset register function
clk: mediatek: reset: Revise structure to control reset register
clk: mediatek: reset: Add return for clock reset register function
clk: mediatek: reset: Add new register reset function with device
clk: mediatek: reset: Add support for input offset and bit from DT
clk: mediatek: reset: Add reset support for simple probe
dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock
dt-binding: mt8192: Add infra_ao reset bit
dt-bindings: arm: mediatek: Add #reset-cells property for MT8195-sys-clock
dt-binding: mt8195: Add infra_ao reset bit
clk: mediatek: reset: Add infra_ao reset support for MT8192
clk: mediatek: reset: Add infra_ao reset support for MT8195
arm64: dts: mediatek: Add infra #reset-cells property for MT8192
.../mediatek/mediatek,mt8192-sys-clock.yaml | 3 +
.../mediatek/mediatek,mt8195-sys-clock.yaml | 3 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1 +
drivers/clk/mediatek/clk-mt2701-eth.c | 8 +-
drivers/clk/mediatek/clk-mt2701-g3d.c | 8 +-
drivers/clk/mediatek/clk-mt2701-hif.c | 8 +-
drivers/clk/mediatek/clk-mt2701.c | 19 +-
drivers/clk/mediatek/clk-mt2712.c | 19 +-
drivers/clk/mediatek/clk-mt7622-eth.c | 8 +-
drivers/clk/mediatek/clk-mt7622-hif.c | 10 +-
drivers/clk/mediatek/clk-mt7622.c | 19 +-
drivers/clk/mediatek/clk-mt7629-eth.c | 8 +-
drivers/clk/mediatek/clk-mt7629-hif.c | 10 +-
drivers/clk/mediatek/clk-mt8135.c | 19 +-
drivers/clk/mediatek/clk-mt8173.c | 19 +-
drivers/clk/mediatek/clk-mt8183.c | 8 +-
drivers/clk/mediatek/clk-mt8192.c | 11 +
drivers/clk/mediatek/clk-mt8195-infra_ao.c | 8 +
drivers/clk/mediatek/clk-mtk.c | 7 +
drivers/clk/mediatek/clk-mtk.h | 9 +-
drivers/clk/mediatek/reset.c | 202 +++++++++++++-----
drivers/clk/mediatek/reset.h | 36 ++++
include/dt-bindings/reset/mt8192-resets.h | 10 +
include/dt-bindings/reset/mt8195-resets.h | 7 +
24 files changed, 381 insertions(+), 79 deletions(-)
create mode 100644 drivers/clk/mediatek/reset.h
--
2.18.0
next reply other threads:[~2022-04-22 6:02 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-22 6:01 Rex-BC Chen [this message]
2022-04-22 6:01 ` [PATCH V3 01/17] clk: mediatek: reset: Add reset.h Rex-BC Chen
2022-04-26 9:33 ` AngeloGioacchino Del Regno
2022-04-22 6:01 ` [PATCH V3 02/17] clk: mediatek: reset: Fix written reset bit offset Rex-BC Chen
2022-04-22 6:01 ` [PATCH V3 03/17] clk: mediatek: reset: Refine and reorder functions in reset.c Rex-BC Chen
2022-04-26 9:34 ` AngeloGioacchino Del Regno
2022-04-22 6:01 ` [PATCH V3 04/17] clk: mediatek: reset: Extract common drivers to update function Rex-BC Chen
2022-04-26 9:34 ` AngeloGioacchino Del Regno
2022-04-22 6:01 ` [PATCH V3 05/17] clk: mediatek: reset: Merge and revise reset register function Rex-BC Chen
2022-04-26 9:34 ` AngeloGioacchino Del Regno
2022-04-22 6:01 ` [PATCH V3 06/17] clk: mediatek: reset: Revise structure to control reset register Rex-BC Chen
2022-04-26 9:34 ` AngeloGioacchino Del Regno
2022-04-22 6:01 ` [PATCH V3 07/17] clk: mediatek: reset: Add return for clock reset register function Rex-BC Chen
2022-04-26 9:34 ` AngeloGioacchino Del Regno
2022-04-22 6:01 ` [PATCH V3 08/17] clk: mediatek: reset: Add new register reset function with device Rex-BC Chen
2022-04-26 9:34 ` AngeloGioacchino Del Regno
2022-04-22 6:01 ` [PATCH V3 09/17] clk: mediatek: reset: Add support for input offset and bit from DT Rex-BC Chen
2022-04-22 6:01 ` [PATCH V3 10/17] clk: mediatek: reset: Add reset support for simple probe Rex-BC Chen
2022-04-22 6:01 ` [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock Rex-BC Chen
2022-04-23 10:27 ` Krzysztof Kozlowski
2022-04-25 2:37 ` Rex-BC Chen
2022-04-25 7:44 ` Krzysztof Kozlowski
2022-04-26 8:24 ` Rex-BC Chen
2022-04-22 6:01 ` [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit Rex-BC Chen
2022-04-23 10:28 ` Krzysztof Kozlowski
2022-04-25 5:01 ` Rex-BC Chen
2022-04-25 7:52 ` Krzysztof Kozlowski
2022-04-26 8:23 ` Rex-BC Chen
2022-04-28 6:40 ` Krzysztof Kozlowski
2022-04-28 6:48 ` Rex-BC Chen
2022-04-28 7:23 ` Krzysztof Kozlowski
2022-04-28 7:36 ` Rex-BC Chen
2022-04-22 6:01 ` [PATCH V3 13/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8195-sys-clock Rex-BC Chen
2022-04-23 10:28 ` Krzysztof Kozlowski
2022-04-22 6:01 ` [PATCH V3 14/17] dt-binding: mt8195: Add infra_ao reset bit Rex-BC Chen
2022-04-23 10:29 ` Krzysztof Kozlowski
2022-04-22 6:01 ` [PATCH V3 15/17] clk: mediatek: reset: Add infra_ao reset support for MT8192 Rex-BC Chen
2022-04-22 6:01 ` [PATCH V3 16/17] clk: mediatek: reset: Add infra_ao reset support for MT8195 Rex-BC Chen
2022-04-22 6:01 ` [PATCH V3 17/17] arm64: dts: mediatek: Add infra #reset-cells property for MT8192 Rex-BC Chen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220422060152.13534-1-rex-bc.chen@mediatek.com \
--to=rex-bc.chen@mediatek.com \
--cc=Project_Global_Chrome_Upstream_Group@mediatek.com \
--cc=angelogioacchino.delregno@collabora.com \
--cc=chun-jie.chen@mediatek.com \
--cc=devicetree@vger.kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=mturquette@baylibre.com \
--cc=p.zabel@pengutronix.de \
--cc=robh+dt@kernel.org \
--cc=runyang.chen@mediatek.com \
--cc=sboyd@kernel.org \
--cc=wenst@chromium.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).