From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9F4FC433EF for ; Mon, 2 May 2022 07:05:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245114AbiEBHJO (ORCPT ); Mon, 2 May 2022 03:09:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1383553AbiEBHJL (ORCPT ); Mon, 2 May 2022 03:09:11 -0400 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 210381A833 for ; Mon, 2 May 2022 00:05:42 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id y14so11627767pfe.10 for ; Mon, 02 May 2022 00:05:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=rdByZ8KQgf5Y1P4UIluf0Nh1xDaQSCS9cES1A4+NlYo=; b=TT0zI40EWySsH971ELVmxDz4QSEhRgxKT530c547Zs96TSPXaKl2Zz3hhd9kcrVUr6 oCfWvoItHskc3tm/NeUvl9ZN5ITlyBtNNtabeaPVTKVPdIrcu6ApaZSAU+hCxdwaYeMC uXh5dFxcCDp+KHpxg+eSHNv6y+mEZlTSvGw0rvU6Pe9t/y+ZKEp3oeqoI5P8SPlwaIzc sBA3VCFOIgjIPQDLKJKPcmOz98J8EcLMRK/PkpWs0GFOG+I+TAhDHDPdkz5fstwrzTQg V4TkPlBxoHXue0usUGMOCfHE4FOnzJTfapxq809FHrzVl95mcRTP0T624CcHb615h6Eg UUzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=rdByZ8KQgf5Y1P4UIluf0Nh1xDaQSCS9cES1A4+NlYo=; b=iAfciB+KKsXSAFOq3BpTBhl6jbsDZATiGK4KwceiteaEU4ekfCLZ6EOkhIGty8ZhJ0 pTYscvSuPkWL/DiWCvclsf/XvOrkhrCqGo+ZRLCekMFokpp9RNYzUZtuN/pRrPEZFMUS l0SZ+di4HBzdSGL4na46ThJUlICyAttxidcJdowoNXvvET570Rg+3CJ4SVjeAdfPflsL lV+n867BqkT9j83FC4XPAJ36yGVRPKMDIS6KoAzo27DNTbqf9y4V1xXWtwrWTiYazvnP mXaHxRiWQHKUVAZ9rbai0sRL5g9tE90J1Xd7XZyitxI3KXUH51s9mjTVb+7EVTU5aOzx XAvg== X-Gm-Message-State: AOAM533PCvDkiH7VayJ4qrY1SsJys7ToN8XnpxOoujJcFjpgZMYF2UaX rx+FE2y7o0GHxI5KDdf1/AGR X-Google-Smtp-Source: ABdhPJyZFmY6tnT/+2kqaW27f44XWOEgl2UR/xzH0VRsYuQ3JTUnoYS7oFZ/MqZ9HE2HgdIwnNP0vQ== X-Received: by 2002:a05:6a00:1391:b0:50d:e125:e3c with SMTP id t17-20020a056a00139100b0050de1250e3cmr5473344pfg.75.1651475142204; Mon, 02 May 2022 00:05:42 -0700 (PDT) Received: from thinkpad ([27.111.75.99]) by smtp.gmail.com with ESMTPSA id x21-20020a62fb15000000b0050dc7628155sm3946187pfm.47.2022.05.02.00.05.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 May 2022 00:05:41 -0700 (PDT) Date: Mon, 2 May 2022 12:35:36 +0530 From: Manivannan Sadhasivam To: Kaushal Kumar Cc: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/4] ARM: dts: qcom: sdx65: Add QPIC NAND support Message-ID: <20220502070536.GC5053@thinkpad> References: <1651332610-6334-1-git-send-email-quic_kaushalk@quicinc.com> <1651332610-6334-3-git-send-email-quic_kaushalk@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1651332610-6334-3-git-send-email-quic_kaushalk@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Sat, Apr 30, 2022 at 08:30:08AM -0700, Kaushal Kumar wrote: > Add devicetree node to enable support for QPIC > NAND controller on Qualcomm SDX65 platform. > Since there is no "aon" clock in SDX65, a dummy > clock is provided. > > Signed-off-by: Kaushal Kumar Reviewed-by: Manivannan Sadhasivam Thanks, Mani > --- > arch/arm/boot/dts/qcom-sdx65.dtsi | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi > index d6a6087..a75e9f1 100644 > --- a/arch/arm/boot/dts/qcom-sdx65.dtsi > +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi > @@ -37,6 +37,12 @@ > clock-output-names = "sleep_clk"; > #clock-cells = <0>; > }; > + > + nand_clk_dummy: nand-clk-dummy { > + compatible = "fixed-clock"; > + clock-frequency = <32764>; > + #clock-cells = <0>; > + }; > }; > > cpus { > @@ -211,6 +217,22 @@ > status = "disabled"; > }; > > + qpic_nand: nand-controller@1b30000 { > + compatible = "qcom,sdx55-nand"; > + reg = <0x01b30000 0x10000>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&rpmhcc RPMH_QPIC_CLK>, > + <&nand_clk_dummy>; > + clock-names = "core", "aon"; > + > + dmas = <&qpic_bam 0>, > + <&qpic_bam 1>, > + <&qpic_bam 2>; > + dma-names = "tx", "rx", "cmd"; > + status = "disabled"; > + }; > + > tcsr_mutex: hwlock@1f40000 { > compatible = "qcom,tcsr-mutex"; > reg = <0x01f40000 0x40000>; > -- > 2.7.4 >