[PATCH 0/9] Add Renesas RZ/V2M Ethernet support

[PATCH 0/9] Add Renesas RZ/V2M Ethernet support

[Phil Edworthy]

The RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB, though
some small parts are the same as R-Car Gen2.
Other differences are:
* It has separate data (DI), error (Line 1) and management (Line 2) irqs
  rather than one irq for all three.
* Instead of using the High-speed peripheral bus clock for gPTP, it has
  a separate gPTP reference clock.

The dts patches depend on v4 of the following patch set:
"Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support"

Phil Edworthy (9):
  clk: renesas: r9a09g011: Add eth clock and reset entries
  dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC
  ravb: Separate use of GIC reg for PTME from multi_irqs
  ravb: Separate handling of irq enable/disable regs into feature
  ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs
  ravb: Use separate clock for gPTP
  ravb: Add support for RZ/V2M
  arm64: dts: renesas: r9a09g011: Add ethernet nodes
  arm64: dts: renesas: rzv2m evk: Enable ethernet

 .../bindings/net/renesas,etheravb.yaml        | 82 ++++++++++++-----
 .../boot/dts/renesas/r9a09g011-v2mevk2.dts    | 14 +++
 arch/arm64/boot/dts/renesas/r9a09g011.dtsi    | 51 +++++++++++
 drivers/clk/renesas/r9a09g011-cpg.c           | 14 +--
 drivers/net/ethernet/renesas/ravb.h           |  7 ++
 drivers/net/ethernet/renesas/ravb_main.c      | 89 +++++++++++++++++--
 drivers/net/ethernet/renesas/ravb_ptp.c       |  4 +-
 7 files changed, 228 insertions(+), 33 deletions(-)

-- 
2.32.0

[PATCH 2/9] dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC

[Phil Edworthy]

Document the Ethernet AVB IP found on RZ/V2M SoC.
It includes the Ethernet controller (E-MAC) and Dedicated Direct memory
access controller (DMAC) for transferring transmitted Ethernet frames
to and received Ethernet frames from respective storage areas in the
URAM at high speed.
The AVB-DMAC is compliant with IEEE 802.1BA, IEEE 802.1AS timing and
synchronization protocol, IEEE 802.1Qav real-time transfer, and the
IEEE 802.1Qat stream reservation protocol.

R-Car has a pair of combined interrupt lines:
 ch22 = Line0_DiA | Line1_A | Line2_A
 ch23 = Line0_DiB | Line1_B | Line2_B
Line0 for descriptor interrupts.
Line1 for error related interrupts (which we call err_a and err_b).
Line2 for management and gPTP related interrupts (mgmt_a and mgmt_b).

RZ/V2M hardware has separate interrupt lines for each of these, but
we keep the "ch22" name for Line0_DiA. We also keep the "ch24" name
for the Line3 (MAC) interrupt.

It has 3 clocks; the main AXI clock, the AMBA CHI clock and a gPTP
reference clock.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../bindings/net/renesas,etheravb.yaml        | 82 ++++++++++++++-----
 1 file changed, 61 insertions(+), 21 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
index ee2ccacc39ff..6c5172ff2b18 100644
--- a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
+++ b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
@@ -43,6 +43,11 @@ properties:
               - renesas,etheravb-r8a779a0     # R-Car V3U
           - const: renesas,etheravb-rcar-gen3 # R-Car Gen3 and RZ/G2
 
+      - items:
+          - enum:
+              - renesas,etheravb-r9a09g011 # RZ/V2M
+          - const: renesas,etheravb-rzv2m  # RZ/V2M compatible
+
       - items:
           - enum:
               - renesas,r9a07g043-gbeth # RZ/G2UL
@@ -160,16 +165,33 @@ allOf:
             - const: arp_ns
         rx-internal-delay-ps: false
     else:
-      properties:
-        interrupts:
-          minItems: 25
-          maxItems: 25
-        interrupt-names:
-          items:
-            pattern: '^ch[0-9]+$'
-      required:
-        - interrupt-names
-        - rx-internal-delay-ps
+      if:
+        properties:
+          compatible:
+            contains:
+              const: renesas,etheravb-rzv2m
+      then:
+        properties:
+          interrupts:
+            minItems: 29
+            maxItems: 29
+          interrupt-names:
+            items:
+              pattern: '^(ch[0-9]+)|dib|err_a|err_b|mgmt_a|mgmt_b$'
+          rx-internal-delay-ps: false
+        required:
+          - interrupt-names
+      else:
+        properties:
+          interrupts:
+            minItems: 25
+            maxItems: 25
+          interrupt-names:
+            items:
+              pattern: '^ch[0-9]+$'
+        required:
+          - interrupt-names
+          - rx-internal-delay-ps
 
   - if:
       properties:
@@ -231,17 +253,35 @@ allOf:
             - const: chi
             - const: refclk
     else:
-      properties:
-        clocks:
-          minItems: 1
-          items:
-            - description: AVB functional clock
-            - description: Optional TXC reference clock
-        clock-names:
-          minItems: 1
-          items:
-            - const: fck
-            - const: refclk
+      if:
+        properties:
+          compatible:
+            contains:
+              const: renesas,etheravb-rzv2m
+      then:
+        properties:
+          clocks:
+            items:
+              - description: Main clock
+              - description: Coherent Hub Interface clock
+              - description: gPTP reference clock
+          clock-names:
+            items:
+              - const: axi
+              - const: chi
+              - const: gptp
+      else:
+        properties:
+          clocks:
+            minItems: 1
+            items:
+              - description: AVB functional clock
+              - description: Optional TXC reference clock
+          clock-names:
+            minItems: 1
+            items:
+              - const: fck
+              - const: refclk
 
 additionalProperties: false
 
-- 
2.32.0

[PATCH 8/9] arm64: dts: renesas: r9a09g011: Add ethernet nodes

[Phil Edworthy]

Add Ethernet nodes to SoC dtsi.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 51 ++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
index 27810f4ad4cb..5948d4f0047b 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
@@ -62,6 +62,57 @@ gic: interrupt-controller@82000000 {
 			clock-names = "clk";
 		};
 
+		avb: ethernet@a3300000 {
+			compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m";
+			reg = <0 0xa3300000 0 0x800>;
+			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, /* ch0: Rx0 BE */
+				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, /* ch1: Rx1 NC */
+				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* ch18: Tx0 BE */
+				     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* ch19: Tx1 NC */
+				     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* ch22: DiA */
+				     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* DiB */
+				     <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, /* Line1_A */
+				     <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, /* Line1_B */
+				     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, /* Line2_A */
+				     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* Line2_B */
+				     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; /* ch24: Line3 MAC */
+			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7",
+					  "ch8", "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15",
+					  "ch16", "ch17", "ch18", "ch19",
+					  "ch20", "ch21", "ch22", "dib",
+					  "err_a", "err_b", "mgmt_a", "mgmt_b",
+					  "ch24";
+			clocks = <&cpg CPG_MOD R9A09G011_ETH0_CLK_AXI>,
+				 <&cpg CPG_MOD R9A09G011_ETH0_CLK_CHI>,
+				 <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>;
+			clock-names = "axi", "chi", "gptp";
+			resets = <&cpg R9A09G011_ETH0_RST_HW_N>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disable";
+		};
+
 		cpg: clock-controller@a3500000 {
 			compatible = "renesas,r9a09g011-cpg";
 			reg = <0 0xa3500000 0 0x1000>;
-- 
2.32.0

[PATCH 9/9] arm64: dts: renesas: rzv2m evk: Enable ethernet

[Phil Edworthy]

Enable Ethernet interface on RZ/V2M EVK.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
index 41cba82c2252..ec7099211cab 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
@@ -14,6 +14,7 @@ / {
 
 	aliases {
 		serial0 = &uart0;
+		ethernet0 = &avb;
 	};
 
 	chosen {
@@ -42,3 +43,16 @@ &extal_clk {
 &uart0 {
 	status = "okay";
 };
+
+&avb {
+	renesas,no-ether-link;
+	phy-handle = <&phy0>;
+	phy-mode = "gmii";
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0022.1622",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
+};
-- 
2.32.0

Re: [PATCH 0/9] Add Renesas RZ/V2M Ethernet support

[Jakub Kicinski]

On Wed,  4 May 2022 15:54:45 +0100 Phil Edworthy wrote:
> The RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB, though
> some small parts are the same as R-Car Gen2.
> Other differences are:
> * It has separate data (DI), error (Line 1) and management (Line 2) irqs
>   rather than one irq for all three.
> * Instead of using the High-speed peripheral bus clock for gPTP, it has
>   a separate gPTP reference clock.
> 
> The dts patches depend on v4 of the following patch set:
> "Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support"
> 
> Phil Edworthy (9):
>   clk: renesas: r9a09g011: Add eth clock and reset entries
>   dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC
>   ravb: Separate use of GIC reg for PTME from multi_irqs
>   ravb: Separate handling of irq enable/disable regs into feature
>   ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs
>   ravb: Use separate clock for gPTP
>   ravb: Add support for RZ/V2M
>   arm64: dts: renesas: r9a09g011: Add ethernet nodes
>   arm64: dts: renesas: rzv2m evk: Enable ethernet

How are you expecting this to be merged?

I think you should drop the first (clk) patch from this series 
so we can apply the series to net-next. And route the clk patch 
thru Geert's tree separately? 

Right now patchwork thinks the series is incomplete because it 
hasn't received patch 1.

Re: [PATCH 0/9] Add Renesas RZ/V2M Ethernet support

[Geert Uytterhoeven]

Hi Jakub,

On Thu, May 5, 2022 at 2:58 AM Jakub Kicinski <kuba@kernel.org> wrote:
> On Wed,  4 May 2022 15:54:45 +0100 Phil Edworthy wrote:
> > The RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB, though
> > some small parts are the same as R-Car Gen2.
> > Other differences are:
> > * It has separate data (DI), error (Line 1) and management (Line 2) irqs
> >   rather than one irq for all three.
> > * Instead of using the High-speed peripheral bus clock for gPTP, it has
> >   a separate gPTP reference clock.
> >
> > The dts patches depend on v4 of the following patch set:
> > "Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support"
> >
> > Phil Edworthy (9):
> >   clk: renesas: r9a09g011: Add eth clock and reset entries
> >   dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC
> >   ravb: Separate use of GIC reg for PTME from multi_irqs
> >   ravb: Separate handling of irq enable/disable regs into feature
> >   ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs
> >   ravb: Use separate clock for gPTP
> >   ravb: Add support for RZ/V2M
> >   arm64: dts: renesas: r9a09g011: Add ethernet nodes
> >   arm64: dts: renesas: rzv2m evk: Enable ethernet
>
> How are you expecting this to be merged?
>
> I think you should drop the first (clk) patch from this series
> so we can apply the series to net-next. And route the clk patch
> thru Geert's tree separately?

Same for the last two DTS patches, they should go through the
renesas-devel and SoC trees.

> Right now patchwork thinks the series is incomplete because it
> hasn't received patch 1.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 0/9] Add Renesas RZ/V2M Ethernet support

[Phil Edworthy]

Hi Jakub, Geert,

On 05 May 2022 07:59 Geert Uytterhoeven wrote:
> On Thu, May 5, 2022 at 2:58 AM Jakub Kicinski wrote:
> > On Wed,  4 May 2022 15:54:45 +0100 Phil Edworthy wrote:
> > > The RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB,
> > > though some small parts are the same as R-Car Gen2.
> > > Other differences are:
> > > * It has separate data (DI), error (Line 1) and management (Line 2)
> irqs
> > >   rather than one irq for all three.
> > > * Instead of using the High-speed peripheral bus clock for gPTP, it
> has
> > >   a separate gPTP reference clock.
> > >
> > > The dts patches depend on v4 of the following patch set:
> > > "Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support"
> > >
> > > Phil Edworthy (9):
> > >   clk: renesas: r9a09g011: Add eth clock and reset entries
> > >   dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC
> > >   ravb: Separate use of GIC reg for PTME from multi_irqs
> > >   ravb: Separate handling of irq enable/disable regs into feature
> > >   ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt)
> irqs
> > >   ravb: Use separate clock for gPTP
> > >   ravb: Add support for RZ/V2M
> > >   arm64: dts: renesas: r9a09g011: Add ethernet nodes
> > >   arm64: dts: renesas: rzv2m evk: Enable ethernet
> >
> > How are you expecting this to be merged?
> >
> > I think you should drop the first (clk) patch from this series so we
> > can apply the series to net-next. And route the clk patch thru Geert's
> > tree separately?
> 
> Same for the last two DTS patches, they should go through the renesas-
> devel and SoC trees.
Sorry, I mistakenly assumed this was all going via Geert's tree, but of
course it's not. I'll split the series in two.


> > Right now patchwork thinks the series is incomplete because it hasn't
> > received patch 1.

Thanks
Phil

Re: [PATCH 2/9] dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC

[Sergey Shtylyov]

Hello!

On 5/4/22 5:54 PM, Phil Edworthy wrote:

> Document the Ethernet AVB IP found on RZ/V2M SoC.
> It includes the Ethernet controller (E-MAC) and Dedicated Direct memory
> access controller (DMAC) for transferring transmitted Ethernet frames
> to and received Ethernet frames from respective storage areas in the
> URAM at high speed.

   I think nobody knows what exactly URAM stands for... you better call it
just RAM. :-)

> The AVB-DMAC is compliant with IEEE 802.1BA, IEEE 802.1AS timing and
> synchronization protocol, IEEE 802.1Qav real-time transfer, and the
> IEEE 802.1Qat stream reservation protocol.
> 
> R-Car has a pair of combined interrupt lines:
>  ch22 = Line0_DiA | Line1_A | Line2_A
>  ch23 = Line0_DiB | Line1_B | Line2_B
> Line0 for descriptor interrupts.
> Line1 for error related interrupts (which we call err_a and err_b).
> Line2 for management and gPTP related interrupts (mgmt_a and mgmt_b).
> 
> RZ/V2M hardware has separate interrupt lines for each of these, but
> we keep the "ch22" name for Line0_DiA.

   Not sure I agree here...
   BTW, aren't the interrupts called "Ethernet ABV.ch<n>" (as on R-Car gen3)
in your (complete?) manual?

> We also keep the "ch24" name for the Line3 (MAC) interrupt.
> 
> It has 3 clocks; the main AXI clock, the AMBA CHI clock and a gPTP

   Could you spell out CHI like below?

> reference clock.
> 
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
[...]

MBR, Sergey

RE: [PATCH 2/9] dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC

[Phil Edworthy]

Hi Sergey,

On 07 May 2022 19:21 Sergey Shtylyov wrote:
> On 5/4/22 5:54 PM, Phil Edworthy wrote:
> 
> > Document the Ethernet AVB IP found on RZ/V2M SoC.
> > It includes the Ethernet controller (E-MAC) and Dedicated Direct memory
> > access controller (DMAC) for transferring transmitted Ethernet frames
> > to and received Ethernet frames from respective storage areas in the
> > URAM at high speed.
> 
>    I think nobody knows what exactly URAM stands for... you better call it
> just RAM. :-)
Going point!

 
> > The AVB-DMAC is compliant with IEEE 802.1BA, IEEE 802.1AS timing and
> > synchronization protocol, IEEE 802.1Qav real-time transfer, and the
> > IEEE 802.1Qat stream reservation protocol.
> >
> > R-Car has a pair of combined interrupt lines:
> >  ch22 = Line0_DiA | Line1_A | Line2_A
> >  ch23 = Line0_DiB | Line1_B | Line2_B
> > Line0 for descriptor interrupts.
> > Line1 for error related interrupts (which we call err_a and err_b).
> > Line2 for management and gPTP related interrupts (mgmt_a and mgmt_b).
> >
> > RZ/V2M hardware has separate interrupt lines for each of these, but
> > we keep the "ch22" name for Line0_DiA.
> 
>    Not sure I agree here...
Ok, I'll use "dia" instead of ch22, and "line3" instead of ch24 on rz/v2m.
Is that ok?


>    BTW, aren't the interrupts called "Ethernet ABV.ch<n>" (as on R-Car
> gen3)
> in your (complete?) manual?
No, they are:
pif_intr_line_0_rx_n[0..17] for Line0_Rx[0..17] 
pif_intr_line_0_tx_n[0..3]  for Line0_Tx[0..3]
pif_intr_line_0_dia_n       for Line0_DiA
pif_intr_line_0_dib_n       for Line0_DiB
pif_intr_line_1_a_n         for Line1_A
pif_intr_line_1_b_n         for Line1_B
pif_intr_line_2_a_n         for Line2_A
pif_intr_line_2_b_n         for Line2_B
pif_intr_line_3_n           for Line3

The full HW manual is available, but an NDA is required:
https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output#document
"[NDA Required] RZ/V2M User's Manual: Hardware (Additional document)"


> > We also keep the "ch24" name for the Line3 (MAC) interrupt.
> >
> > It has 3 clocks; the main AXI clock, the AMBA CHI clock and a gPTP
> 
>    Could you spell out CHI like below?
Will do.


> > reference clock.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> [...]

Thanks
Phil