From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70D8BC4707E for ; Thu, 5 May 2022 09:12:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352023AbiEEJQS (ORCPT ); Thu, 5 May 2022 05:16:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351972AbiEEJQR (ORCPT ); Thu, 5 May 2022 05:16:17 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4332C4C790 for ; Thu, 5 May 2022 02:12:38 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id 4so4763389ljw.11 for ; Thu, 05 May 2022 02:12:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CTHkilprIvL9A/8ur+bw1pjnP/4ABBDDnOBt355kY54=; b=MtVHPH+tkf1YNfY9FifF4Ub1Vf/DvqV7wJV7BBt6pPpe0WSzEFCk7IN+oEobRWnfF4 Ge+x9KE0pRCW/1TAdxY5AqywQbtXZA7lIMb7I+b7Ima6BdjJlFnRcfadTqUtQohlYLT1 ihrF+FtM96PeZ9GKH/MuOWBlQTTmG8bjcKIIG/xbX4QtPAD3A2n3Q07zEDSXma+rFnDF 8UJD05ozoC5+ur6v86Ee3iBiSfp4r2+a7L8U27ZqcVPgptI9CkpYh5IZYAfqkTz2+JUT Z9K+MDu+I7bkh0serbw8Ugy2r9u/tUvIsrEUsDv9uhRcPRIE3STky0krP3b3QE6GTL8P X9rA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CTHkilprIvL9A/8ur+bw1pjnP/4ABBDDnOBt355kY54=; b=WNKBxFUgGZuBESY3Hq/x2MpTUEi35iKGuZJNgmUrKzagW+aB0KWMwhgC2JC0cFqYtI chtka/FulZ3kILUUybvpPYGN8yr9JYjp1Lwx+Wf1Fma8ExgD0tF/K/kuVR9Z94hQeSQO DsPO60FF548ltBeOcBd7UUk+KOjn0rABacto5vcmKK8WsRPPdwqi53c65dpdefF1U/aU dcxyq34m3Ir0Oj00ux+4R9qvXeQIFvMXqg0w7Ty20Jx1+0x8jF1FOTaUFOrqsLJHvATC mfXEqtywK6ZcvThCgLfg53v3qJhg4N3r/W2P5cCnt3xWqU0X+2ml/N0DKdrkEKckAn3b V6PQ== X-Gm-Message-State: AOAM530tED11jUqiXAqjmitPDuOPryod6wfXRBa8rufv6fS/ZXGZoGaR f99xSgKtt4016ioQ/TQc7zmxKQ== X-Google-Smtp-Source: ABdhPJw+zrP5UZN20F6mshaehcVua4TB0NWgYUNpRbfWLql7Hgdt0MsCQPsZYuzdjNU45bQY3YP2MQ== X-Received: by 2002:a2e:b88f:0:b0:24f:4fbc:6628 with SMTP id r15-20020a2eb88f000000b0024f4fbc6628mr12830576ljp.38.1651741956466; Thu, 05 May 2022 02:12:36 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v26-20020ac2593a000000b0047255d211e8sm133564lfi.279.2022.05.05.02.12.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:36 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v6 6/7] dt-bindings: PCI: qcom: Support additional MSI interrupts Date: Thu, 5 May 2022 12:12:30 +0300 Message-Id: <20220505091231.1308963-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220505091231.1308963-1-dmitry.baryshkov@linaro.org> References: <20220505091231.1308963-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Document mapping of additional interrupts. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/pci/qcom,pcie.yaml | 45 ++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 0b69b12b849e..fd3290e0e220 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -43,11 +43,20 @@ properties: maxItems: 5 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 8 interrupt-names: + minItems: 1 items: - const: msi + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + - const: msi8 # Common definitions for clocks, clock-names and reset. # Platform constraints are described later. @@ -623,6 +632,40 @@ allOf: - resets - reset-names + # On newer chipsets support either 1 or 8 msi interrupts + # On older chipsets it's always 1 msi interrupt + - if: + properties: + compatibles: + contains: + enum: + - qcom,pcie-msm8996 + - qcom,pcie-sc7280 + - qcom,pcie-sc8180x + - qcom,pcie-sdm845 + - qcom,pcie-sm8150 + - qcom,pcie-sm8250 + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + then: + oneOf: + - properties: + interrupts: + maxItems: 1 + interrupt-names: + maxItems: 1 + - properties: + interrupts: + minItems: 8 + interrupt-names: + minItems: 8 + else: + properties: + interrupts: + maxItems: 1 + interrupt-names: + maxItems: 1 + unevaluatedProperties: false examples: -- 2.35.1