[PATCH v4 0/2] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support

[PATCH v4 0/2] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support

[Phil Edworthy]

Hello,

RZ/V2M has a dual-core Cortex-A53 (1.0 GHz) CPU and built-in AI
accelerator "DRP-AI" for vision, which is Renesas' original technology.
It also has a 32-bit LPDDR4 interface and video codec (H.264).

The RZ/V2M is used with ISP firmware that runs on one of the Cortex-A53
cores. The firmware is an integral part of the SoC such that the HW
User's Manual documents which of the peripheral modules are used by the
firmware.

Initial patches enables minimal peripherals on Renesas RZ/V2M EVK board
and booted via nfs. Ethernet is broadly compatible with the
etheravb-rcar-gen3 driver, but interrupts need some work so it's not
been included in this patch set.

Below blocks are enabled on Renesas RZ/V2M EVK board:
- memory
- External input clock
- CPG
- UART

Links for SoC and EVK:
[*] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output


Sorry for cross posting the patches to multiple subsystems, as these are
just the dt-binding patches included as part of initial bringup patches.

v4:
 * Removed arm,arch_timer optional clock and reset
 * Removed "optional" from description of renesas,em-uart clock.

v3:
 * Feedback addressed
 * Added patch [0001] for renesas,em-uart dt-bindings RZ/V2M clock for the regs
 * Added patch [0004] for arm,arch_timer dt-bindings optional clock and reset
 * Added patch [0005] for rzg2l clk to move the DEF_MUX array size calc into the macro
 * Added patch [0006] for rzg2l clk to add read-only versions of the macros

v2:
 * Removed SYS dt-bindings patch and corresponding SoC identification
   as we only used the LSI version register. This can be dealt with
   later on.
 * Fixed em-uart dt-bindings.
 * Included reviewed-by tags.

Thanks
Phil

[PATCH v4 1/2] dt-bindings: serial: renesas,em-uart: Add RZ/V2M clock to access the registers

[Phil Edworthy]

The RZ/V2M SoC has an additional clock to access the registers. The HW
manual says this clock should not be touched as it is used by the
"ISP Firmware".

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v4:
 - Removed "optional" from description of clock to access the registers
v3:
 - New patch added
---
 .../bindings/serial/renesas,em-uart.yaml      | 32 +++++++++++++++----
 1 file changed, 25 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
index 332c385618e1..40a03f255666 100644
--- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
@@ -9,9 +9,6 @@ title: Renesas EMMA Mobile UART Interface
 maintainers:
   - Magnus Damm <magnus.damm@gmail.com>
 
-allOf:
-  - $ref: serial.yaml#
-
 properties:
   compatible:
     oneOf:
@@ -29,11 +26,32 @@ properties:
   interrupts:
     maxItems: 1
 
-  clocks:
-    maxItems: 1
+allOf:
+  - $ref: serial.yaml#
 
-  clock-names:
-    const: sclk
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a09g011-uart
+    then:
+      properties:
+        clocks:
+          items:
+            - description: UART functional clock
+            - description: Internal clock to access the registers
+        clock-names:
+          items:
+            - const: sclk
+            - const: pclk
+    else:
+      properties:
+        clocks:
+          items:
+            - description: UART functional clock
+        clock-names:
+          items:
+            - const: sclk
 
 required:
   - compatible
-- 
2.32.0

[PATCH v4 2/2] arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC

[Phil Edworthy]

Details of the SoC can be found here:
https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v4:
 - Removed arm,arch_timer optional clock and reset

v3:
 - Replace CPG_CORE with CPG_MOD
 - Add UART pclk
 - Add gic clk
 - Fix cpg and uart0 register region
 - Remove sys as we are currently not using it and binding not accepted
---
 arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 93 ++++++++++++++++++++++
 1 file changed, 93 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g011.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
new file mode 100644
index 000000000000..27810f4ad4cb
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/V2M SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a09g011-cpg.h>
+
+/ {
+	compatible = "renesas,r9a09g011";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53";
+			reg = <0>;
+			device_type = "cpu";
+			clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
+		};
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gic: interrupt-controller@82000000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x0 0x82010000 0 0x1000>,
+			      <0x0 0x82020000 0 0x20000>,
+			      <0x0 0x82040000 0 0x20000>,
+			      <0x0 0x82060000 0 0x20000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+			clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
+			clock-names = "clk";
+		};
+
+		cpg: clock-controller@a3500000 {
+			compatible = "renesas,r9a09g011-cpg";
+			reg = <0 0xa3500000 0 0x1000>;
+			clocks = <&extal_clk>;
+			clock-names = "extal";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		uart0: serial@a4040000 {
+			compatible = "renesas,r9a09g011-uart", "renesas,em-uart";
+			reg = <0 0xa4040000 0 0x80>;
+			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>,
+				 <&cpg CPG_MOD R9A09G011_URT_PCLK>;
+			clock-names = "sclk", "pclk";
+			status = "disabled";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
-- 
2.32.0

Re: [PATCH v4 1/2] dt-bindings: serial: renesas,em-uart: Add RZ/V2M clock to access the registers

[Rob Herring]

On Wed, May 04, 2022 at 10:44:55AM +0100, Phil Edworthy wrote:
> The RZ/V2M SoC has an additional clock to access the registers. The HW
> manual says this clock should not be touched as it is used by the
> "ISP Firmware".
> 
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v4:
>  - Removed "optional" from description of clock to access the registers
> v3:
>  - New patch added
> ---
>  .../bindings/serial/renesas,em-uart.yaml      | 32 +++++++++++++++----
>  1 file changed, 25 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> index 332c385618e1..40a03f255666 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> @@ -9,9 +9,6 @@ title: Renesas EMMA Mobile UART Interface
>  maintainers:
>    - Magnus Damm <magnus.damm@gmail.com>
>  
> -allOf:
> -  - $ref: serial.yaml#
> -
>  properties:
>    compatible:
>      oneOf:
> @@ -29,11 +26,32 @@ properties:
>    interrupts:
>      maxItems: 1
>  
> -  clocks:
> -    maxItems: 1
> +allOf:
> +  - $ref: serial.yaml#
>  
> -  clock-names:
> -    const: sclk
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a09g011-uart
> +    then:
> +      properties:

> +        clocks:
> +          items:
> +            - description: UART functional clock
> +            - description: Internal clock to access the registers
> +        clock-names:
> +          items:
> +            - const: sclk
> +            - const: pclk

Better to put all this at the top level with 'minItems: 1' and then use 
minItems/maxItems in the if/then schema to define which platforms have 1 
or 2 clocks.

> +    else:
> +      properties:
> +        clocks:
> +          items:
> +            - description: UART functional clock
> +        clock-names:
> +          items:
> +            - const: sclk
>  
>  required:
>    - compatible
> -- 
> 2.32.0
> 
> 

RE: [PATCH v4 1/2] dt-bindings: serial: renesas,em-uart: Add RZ/V2M clock to access the registers

[Phil Edworthy]

Hi Rob,

On 11 May 2022 16:04 Rob Herring wrote:
> On Wed, May 04, 2022 at 10:44:55AM +0100, Phil Edworthy wrote:
> > The RZ/V2M SoC has an additional clock to access the registers. The HW
> > manual says this clock should not be touched as it is used by the
> > "ISP Firmware".
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> > v4:
> >  - Removed "optional" from description of clock to access the registers
> > v3:
> >  - New patch added
> > ---
> >  .../bindings/serial/renesas,em-uart.yaml      | 32 +++++++++++++++----
> >  1 file changed, 25 insertions(+), 7 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/serial/renesas,em-
> uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > index 332c385618e1..40a03f255666 100644
> > --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > @@ -9,9 +9,6 @@ title: Renesas EMMA Mobile UART Interface
> >  maintainers:
> >    - Magnus Damm <magnus.damm@gmail.com>
> >
> > -allOf:
> > -  - $ref: serial.yaml#
> > -
> >  properties:
> >    compatible:
> >      oneOf:
> > @@ -29,11 +26,32 @@ properties:
> >    interrupts:
> >      maxItems: 1
> >
> > -  clocks:
> > -    maxItems: 1
> > +allOf:
> > +  - $ref: serial.yaml#
> >
> > -  clock-names:
> > -    const: sclk
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: renesas,r9a09g011-uart
> > +    then:
> > +      properties:
> 
> > +        clocks:
> > +          items:
> > +            - description: UART functional clock
> > +            - description: Internal clock to access the registers
> > +        clock-names:
> > +          items:
> > +            - const: sclk
> > +            - const: pclk
> 
> Better to put all this at the top level with 'minItems: 1' and then use
> minItems/maxItems in the if/then schema to define which platforms have 1
> or 2 clocks.

Thanks Rob, will do!
Phil


> > +    else:
> > +      properties:
> > +        clocks:
> > +          items:
> > +            - description: UART functional clock
> > +        clock-names:
> > +          items:
> > +            - const: sclk
> >
> >  required:
> >    - compatible
> > --
> > 2.32.0
> >
> >