From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D632C4167B for ; Thu, 12 May 2022 23:44:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359621AbiELXoA (ORCPT ); Thu, 12 May 2022 19:44:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359611AbiELXn4 (ORCPT ); Thu, 12 May 2022 19:43:56 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF12528AB8E for ; Thu, 12 May 2022 16:43:54 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id d15so11736476lfk.5 for ; Thu, 12 May 2022 16:43:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x2qQH918JYdrczWJIIm8XRXT3abBOAyM4GeAzsiuGrc=; b=aJg8B52S+gciOhJywFmn9XfeNsV8s5n1TBGB7xkNP56vkdkaUXtB9h6f+SrGaoFJ3u cPJn2d+dzuWOWr9dkgwql6OSPq1k9SYXGO02g2RgT9+0VKcbq5cisyfM9REnsXxHNBEP uNW/0a7ZvCSgloVwUD/6NpakNX6wX4VuVFfdoysCwYvB35QLqzyWzMvQEOaCvfAY4GCX YmdeVKCR1qNZPR0UlmWzc37YD8g7W7Giq/nWCN982QadAzmCk0qwurDRgfBC1kxhD2/8 XOGBbVxfx2z5MUn4jgl2q7xMU2HGsmIhLj1lJkX9a8G2hJi+CY9Rn+373n2UAOLMnM3G mA0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x2qQH918JYdrczWJIIm8XRXT3abBOAyM4GeAzsiuGrc=; b=6ZfsZYtma9vfLSGxDWJJD202j91x1eOB737v0+LP3TWR8Z8w27Ug1/WSuB4IVY2Hdk keJmgft8IZeKtE3x9rOItwuspg2k/77tmdGOt2F/aBV3s7Yci8mH4rROfDokqg+2uw7W 755D6Lo5CEvrAOPlZ50FHdYl81kxuWs0WwTg9eQXNXnfPsG2rVFAT9oww1lbbbbOPgno C2n6NbkZ4qk0NeJgIbgf/J47Q0aEwXwE9ICnwLT/6y6Ufp0jsJUpRvrBPkNwghP9rAH0 UCOHha5e9r6wWSWBdgiagKPhlUgRKP6j5AuBfa47UtunvLZEwbp4lZ+OMifQbevXSOE/ pOcg== X-Gm-Message-State: AOAM530RtMZl6EMEFZiXkv2ays/SxySQJ4c6RFYAiRR9ySIP6JSs10uM sj6q2l9ZPRTjRJD8VcSnXyjqfA== X-Google-Smtp-Source: ABdhPJz98jmWJlPjffML1K9eGoPwQwUa3ktR8KUeTBeSxmghQv1CjwmSP/FvRmdTDkVWla/1VTtY5A== X-Received: by 2002:a05:6512:5ca:b0:471:f1d6:b183 with SMTP id o10-20020a05651205ca00b00471f1d6b183mr1495975lfo.197.1652399033105; Thu, 12 May 2022 16:43:53 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id u10-20020ac248aa000000b0047255d211b8sm129976lfg.231.2022.05.12.16.43.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 16:43:52 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [RESEND v2 4/8] arm64: dts: qcom: sdm630: fix the qusb2phy ref clock Date: Fri, 13 May 2022 02:43:45 +0300 Message-Id: <20220512234349.2673724-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512234349.2673724-1-dmitry.baryshkov@linaro.org> References: <20220512234349.2673724-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org According to the downstram DT file, the qusb2phy ref clock should be GCC_RX0_USB2_CLKREF_CLK, not GCC_RX1_USB2_CLKREF_CLK. Fixes: c65a4ed2ea8b ("arm64: dts: qcom: sdm630: Add USB configuration") Cc: Konrad Dybcio Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index e8bb170e8b2f..cca56f2fad96 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1262,7 +1262,7 @@ qusb2phy: phy@c012000 { #phy-cells = <0>; clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_RX1_USB2_CLKREF_CLK>; + <&gcc GCC_RX0_USB2_CLKREF_CLK>; clock-names = "cfg_ahb", "ref"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; -- 2.35.1