From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AB5BC433EF for ; Tue, 17 May 2022 15:52:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349332AbiEQPwp (ORCPT ); Tue, 17 May 2022 11:52:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346893AbiEQPwo (ORCPT ); Tue, 17 May 2022 11:52:44 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78B65227; Tue, 17 May 2022 08:52:41 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id 2063A1F44901 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1652802759; bh=VLzWzYuHr/VzEBBJLbkAVVXYd+h4cdCEC+8NQ7kC4JA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=TE9QVuqAXjGy+Z0+mzBT9lESF2kymZU/vtdnDdQpa+fEy+Ahnn/7U/Kb0t4Ga9siQ qY6K1SAUcEVdkJ6C7N9qWt7RTzVN7Ghop87kTcapeCDNbpCOanJhfjJ263OEU4i4R/ JVGX9VlCbFERCSFx87F+qD+s+j9c8XbrgfRwMUSQabVlisK67SIxF/EykUlaEAjbMF iEpgw8wxJx+pZsaZmiNvrdGjZOf/K/MyXeZVO0dXd8CF8Ea0u9lWeXL9Y9gsulir1T /jPuxypQZDjg1aZKFP9H3bHcjFMRhi6qruWysx/WHmXntxuiFa8NACCuPsHTxppIzM scv2j6GelbU0w== Date: Tue, 17 May 2022 11:52:34 -0400 From: =?utf-8?B?TsOtY29sYXMgRi4gUi4gQS4=?= Prado To: Allen-KH Cheng Cc: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Project_Global_Chrome_Upstream_Group@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Chen-Yu Tsai , Ryder Lee , Hui Liu Subject: Re: [PATCH 1/1] arm64: dts: mt8192: Add vcodec lat and core nodes Message-ID: <20220517155234.5sa6vd23x2zrltht@notapiano> References: <20220408104124.31395-1-allen-kh.cheng@mediatek.com> <20220408104124.31395-2-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220408104124.31395-2-allen-kh.cheng@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Apr 08, 2022 at 06:41:24PM +0800, Allen-KH Cheng wrote: > Add vcodec lat and core nodes for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng > Reviewed-by: AngeloGioacchino Del Regno Hi, With the new mt8192 scp.img firmware merged on linux-firmware [1] and the mtk-vcodec decoder support for mt8192 merged in the media tree [2], the DT nodes for the decoder added in this patch are the last missing piece to have the decoder usable on mt8192-based machines. With this patch applied, I was able to run fluster [3] on mt8192-asurada-spherion and obtain the following results: VP8: 59/61 VP9: 249/303 H.264: 92/135 So, Reviewed-by: Nícolas F. R. A. Prado Tested-by: Nícolas F. R. A. Prado Thanks, Nícolas [1] https://lore.kernel.org/all/CA+5PVA43SgXKz5EA6RTk74FxiDALy899G1Rvi_aO=q9Yd_pCKw@mail.gmail.com/ [2] https://lore.kernel.org/all/875b24355315311db3a0c846be5f553b3d0c7498.camel@mediatek.com/ [3] https://github.com/fluendo/fluster > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++ > 1 file changed, 60 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 18a58239d6f1..c7f4b2fbb315 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -1120,6 +1120,66 @@ > power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; > }; > > + vcodec_dec: vcodec-dec@16000000 { > + compatible = "mediatek,mt8192-vcodec-dec"; > + reg = <0 0x16000000 0 0x1000>; > + mediatek,scp = <&scp>; > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0 0 0 0x16000000 0 0x26000>; > + > + vcodec_lat: vcodec-lat@10000 { > + compatible = "mediatek,mtk-vcodec-lat"; > + reg = <0x0 0x10000 0 0x800>; > + interrupts = ; > + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; > + clocks = <&topckgen CLK_TOP_VDEC_SEL>, > + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, > + <&vdecsys_soc CLK_VDEC_SOC_LAT>, > + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, > + <&topckgen CLK_TOP_MAINPLL_D4>; > + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; > + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; > + }; > + > + vcodec_core: vcodec-core@25000 { > + compatible = "mediatek,mtk-vcodec-core"; > + reg = <0 0x25000 0 0x1000>; > + interrupts = ; > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; > + clocks = <&topckgen CLK_TOP_VDEC_SEL>, > + <&vdecsys CLK_VDEC_VDEC>, > + <&vdecsys CLK_VDEC_LAT>, > + <&vdecsys CLK_VDEC_LARB1>, > + <&topckgen CLK_TOP_MAINPLL_D4>; > + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; > + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; > + }; > + }; > + > larb5: larb@1600d000 { > compatible = "mediatek,mt8192-smi-larb"; > reg = <0 0x1600d000 0 0x1000>; > -- > 2.18.0 > >