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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id k22-20020a056870959600b000e686d1386asm313715oao.4.2022.05.17.14.04.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 May 2022 14:04:08 -0700 (PDT) Received: (nullmailer pid 1640028 invoked by uid 1000); Tue, 17 May 2022 21:04:07 -0000 Date: Tue, 17 May 2022 16:04:07 -0500 From: Rob Herring To: Biju Das Cc: Thierry Reding , Lee Jones , Krzysztof Kozlowski , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven , Chris Paterson , Biju Das , Prabhakar Mahadev Lad , linux-renesas-soc@vger.kernel.org Subject: Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG binding Message-ID: <20220517210407.GA1635524-robh@kernel.org> References: <20220510151112.16249-1-biju.das.jz@bp.renesas.com> <20220510151112.16249-2-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220510151112.16249-2-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, May 10, 2022 at 04:11:05PM +0100, Biju Das wrote: > Add device tree bindings for the RZ/G2L Port Output Enable for GPT (POEG). > > Signed-off-by: Biju Das > --- > .../soc/renesas/renesas,rzg2l-poeg.yaml | 65 +++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yaml > > diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yaml > new file mode 100644 > index 000000000000..5737dbf3fa45 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yaml > @@ -0,0 +1,65 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/soc/renesas/renesas,rzg2l-poeg.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Renesas RZ/G2L Port Output Enable for GPT (POEG) > + > +maintainers: > + - Biju Das > + > +description: '|' needed. > + The output pins of the general PWM timer (GPT) can be disabled by using > + the port output enabling function for the GPT (POEG). Specifically, > + either of the following ways can be used. > + * Input level detection of the GTETRGA to GTETRGD pins. > + * Output-disable request from the GPT. > + * Register settings. > + > +properties: > + compatible: > + items: > + - enum: > + - renesas,r9a07g044-poeg # RZ/G2{L,LC} > + - renesas,r9a07g054-poeg # RZ/V2L > + - const: renesas,rzg2l-poeg > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - power-domains > + - resets > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + poeggd: poeg@10049400 { > + compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg"; > + reg = <0x10049400 0x4>; This looks like it is part of some larger block? > + interrupts = ; > + clocks = <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>; > + power-domains = <&cpg>; > + resets = <&cpg R9A07G044_POEG_D_RST>; > + }; > -- > 2.25.1 > >