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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id w10-20020aca620a000000b00325cda1ffb9sm290734oib.56.2022.05.17.17.47.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 May 2022 17:47:07 -0700 (PDT) Received: (nullmailer pid 1965783 invoked by uid 1000); Wed, 18 May 2022 00:47:06 -0000 Date: Tue, 17 May 2022 19:47:06 -0500 From: Rob Herring To: AngeloGioacchino Del Regno Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, y.oudjana@protonmail.com, jason-jh.lin@mediatek.com, ck.hu@mediatek.com, fparent@baylibre.com, rex-bc.chen@mediatek.com, tinghan.shen@mediatek.com, chun-jie.chen@mediatek.com, weiyi.lu@mediatek.com, ikjn@chromium.org, miles.chen@mediatek.com, sam.shih@mediatek.com, wenst@chromium.org, bgolaszewski@baylibre.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, paul.bouchara@somainline.org, kernel@collabora.com Subject: Re: [PATCH 0/5] MediaTek Helio X10 MT6795 - Clock drivers Message-ID: <20220518004706.GA1950724-robh@kernel.org> References: <20220513165050.500831-1-angelogioacchino.delregno@collabora.com> <7ed1b785-389f-9730-4686-bc6b85cc8f6d@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7ed1b785-389f-9730-4686-bc6b85cc8f6d@collabora.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, May 13, 2022 at 06:54:49PM +0200, AngeloGioacchino Del Regno wrote: > Il 13/05/22 18:50, AngeloGioacchino Del Regno ha scritto: > > In an effort to give some love to the apparently forgotten MT6795 SoC, > > I am upstreaming more components that are necessary to support platforms > > powered by this one apart from a simple boot to serial console. > > > > This (very big) series introduces system clock, multimedia clock drivers > > (including resets) for this SoC. > > > > Tested on a MT6795 Sony Xperia M5 (codename "Holly") smartphone. > > > > I forgot to add context to the cover letter for this series, so I'm adding that > in reply to myself. > > This series depends on Chen-Yu's clocks cleanup series (clk_hw) [1] *and* on > Rex-BC's MTK reset binding-cleanup series [2]. > > [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=640122 > [2] https://patchwork.kernel.org/project/linux-mediatek/list/?series=637849 As well as the schema conversions in my tree. So I need to apply some of this? Provide maintainers with details on how exactly a series should be applied if there's a mixture of subsystems, dependencies already applied, and dependencies not yet applied. I'm just going to wait for explicit requests of what I need to apply as there's already too much Mediatek stuff floating around. Last merge window was a mess too. Rob