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From: Rex-BC Chen <rex-bc.chen@mediatek.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
	<matthias.bgg@gmail.com>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>
Cc: <p.zabel@pengutronix.de>,
	<angelogioacchino.delregno@collabora.com>,
	<nfraprado@collabora.com>, <chun-jie.chen@mediatek.com>,
	<wenst@chromium.org>, <runyang.chen@mediatek.com>,
	<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-clk@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	Rex-BC Chen <rex-bc.chen@mediatek.com>
Subject: [RESEND v8 08/19] clk: mediatek: reset: Support inuput argument index mode
Date: Mon, 23 May 2022 17:33:35 +0800	[thread overview]
Message-ID: <20220523093346.28493-9-rex-bc.chen@mediatek.com> (raw)
In-Reply-To: <20220523093346.28493-1-rex-bc.chen@mediatek.com>

There is a large number of mediatek infra reset bits, but we do not use
all of them. In addition, the proper input argement of reset controller
soulde be index.
Therefore, to be compatible with previous drivers and usage, we add
description variables to store the ids which can mapping to index.

To use this mode, we need to put the id in rst_idx_map to map from
index to ids. For example, if we want to input index 1 (this index
is used to set bank 1 bit 14) for svs, we need to declare the reset
controller like this:

In drivers:
static u16 rst_ofs[] = {
        0x120, 0x130, 0x140, 0x150, 0x730,
};

static u16 rst_idx_map[] = {
        0 * 32 + 0,
        1 * 32 + 14,
        ....
};

static const struct mtk_clk_rst_desc clk_rst_desc = {
        .version = MTK_RST_SET_CLR,
        .rst_bank_ofs = rst_ofs,
        .rst_bank_nr = ARRAY_SIZE(rst_ofs),
        .rst_idx_map = rst_idx_map,
        .rst_idx_map_nr = ARRAY_SIZE(rst_idx_map),
};

In dts:
svs: {
        ...
        resets = <&infra 1>;
        ...
};

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
---
 drivers/clk/mediatek/reset.c | 21 ++++++++++++++++++++-
 drivers/clk/mediatek/reset.h |  5 +++++
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 11b2f74f121d..89e617ea6393 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -98,6 +98,18 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
 	.reset = mtk_reset_set_clr,
 };
 
+static int reset_xlate(struct reset_controller_dev *rcdev,
+		       const struct of_phandle_args *reset_spec)
+{
+	struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
+
+	if (reset_spec->args[0] >= rcdev->nr_resets ||
+	    reset_spec->args[0] >= data->desc->rst_idx_map_nr)
+		return -EINVAL;
+
+	return data->desc->rst_idx_map[reset_spec->args[0]];
+}
+
 void mtk_register_reset_controller(struct device_node *np,
 				   const struct mtk_clk_rst_desc *desc)
 {
@@ -136,10 +148,17 @@ void mtk_register_reset_controller(struct device_node *np,
 	data->desc = desc;
 	data->regmap = regmap;
 	data->rcdev.owner = THIS_MODULE;
-	data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK;
 	data->rcdev.ops = rcops;
 	data->rcdev.of_node = np;
 
+	if (data->desc->rst_idx_map_nr > 0) {
+		data->rcdev.of_reset_n_cells = 1;
+		data->rcdev.nr_resets = desc->rst_idx_map_nr;
+		data->rcdev.of_xlate = reset_xlate;
+	} else {
+		data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK;
+	}
+
 	ret = reset_controller_register(&data->rcdev);
 	if (ret) {
 		pr_err("could not register reset controller: %d\n", ret);
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index d991510ae2d8..cc847c67a2fc 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -28,11 +28,16 @@ enum mtk_reset_version {
  * @version: Reset version which is defined in enum mtk_reset_version.
  * @rst_bank_ofs: Pointer to an array containing base offsets of the reset register.
  * @rst_bank_nr: Quantity of reset bank.
+ * @rst_idx_map:Pointer to an array containing ids if input argument is index.
+ *		This array is not necessary if our input argument does not mean index.
+ * @rst_idx_map_nr: Quantity of reset index map.
  */
 struct mtk_clk_rst_desc {
 	enum mtk_reset_version version;
 	u16 *rst_bank_ofs;
 	u32 rst_bank_nr;
+	u16 *rst_idx_map;
+	u32 rst_idx_map_nr;
 };
 
 /**
-- 
2.18.0


  parent reply	other threads:[~2022-05-23  9:34 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-23  9:33 [RESEND v8 00/19] Cleanup MediaTek clk reset drivers and support SoCs Rex-BC Chen
2022-05-23  9:33 ` [RESEND v8 01/19] clk: mediatek: reset: Add reset.h Rex-BC Chen
2022-06-16  1:50   ` Stephen Boyd
2022-05-23  9:33 ` [RESEND v8 02/19] clk: mediatek: reset: Fix written reset bit offset Rex-BC Chen
2022-06-16  1:50   ` Stephen Boyd
2022-05-23  9:33 ` [RESEND v8 03/19] clk: mediatek: reset: Refine and reorder functions in reset.c Rex-BC Chen
2022-06-16  1:50   ` Stephen Boyd
2022-05-23  9:33 ` [RESEND v8 04/19] clk: mediatek: reset: Extract common drivers to update function Rex-BC Chen
2022-06-16  1:50   ` Stephen Boyd
2022-05-23  9:33 ` [RESEND v8 05/19] clk: mediatek: reset: Merge and revise reset register function Rex-BC Chen
2022-06-16  1:51   ` Stephen Boyd
2022-05-23  9:33 ` [RESEND v8 06/19] clk: mediatek: reset: Revise structure to control reset register Rex-BC Chen
2022-06-16  1:51   ` Stephen Boyd
2022-05-23  9:33 ` [RESEND v8 07/19] clk: mediatek: reset: Support nonsequence base offsets of reset registers Rex-BC Chen
2022-06-16  1:51   ` Stephen Boyd
2022-05-23  9:33 ` Rex-BC Chen [this message]
2022-06-16  1:51   ` [RESEND v8 08/19] clk: mediatek: reset: Support inuput argument index mode Stephen Boyd
2022-05-23  9:33 ` [RESEND v8 09/19] clk: mediatek: reset: Change return type for clock reset register function Rex-BC Chen
2022-06-16  1:52   ` Stephen Boyd
2022-05-23  9:33 ` [RESEND v8 10/19] clk: mediatek: reset: Add new register reset function with device Rex-BC Chen
2022-06-16  1:52   ` Stephen Boyd
2022-05-23  9:33 ` [RESEND v8 11/19] clk: mediatek: reset: Add reset support for simple probe Rex-BC Chen
2022-06-16  1:53   ` Stephen Boyd
2022-05-23  9:33 ` [RESEND v8 12/19] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195 Rex-BC Chen
2022-06-16  1:53   ` Stephen Boyd
2022-05-23  9:33 ` [RESEND v8 13/19] dt-bindings: reset: mediatek: Add infra_ao reset index " Rex-BC Chen
2022-06-16  1:53   ` Stephen Boyd
2022-05-23  9:33 ` [RESEND v8 14/19] clk: mediatek: reset: Add infra_ao reset support " Rex-BC Chen
2022-06-16  1:55   ` Stephen Boyd
2022-05-23  9:33 ` [RESEND v8 15/19] arm64: dts: mediatek: Add infra #reset-cells property for MT8192 Rex-BC Chen
2022-05-23  9:33 ` [RESEND v8 16/19] arm64: dts: mediatek: Add infra #reset-cells property for MT8195 Rex-BC Chen
2022-05-23  9:33 ` [RESEND v8 17/19] dt-bindings: reset: mediatek: Add infra_ao reset index for MT8186 Rex-BC Chen
2022-06-16  1:55   ` Stephen Boyd
2022-05-23  9:33 ` [RESEND v8 18/19] dt-bindings: arm: mediatek: Add #reset-cells property " Rex-BC Chen
2022-06-16  1:55   ` Stephen Boyd
2022-05-23  9:33 ` [RESEND v8 19/19] clk: mediatek: reset: Add infra_ao reset support " Rex-BC Chen
2022-06-16  1:55   ` Stephen Boyd
2022-05-23 10:28 ` [RESEND v8 00/19] Cleanup MediaTek clk reset drivers and support SoCs AngeloGioacchino Del Regno
2022-06-13  5:26 ` Rex-BC Chen
2022-06-16  1:57   ` Stephen Boyd

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