From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30EC8C433FE for ; Wed, 1 Jun 2022 03:54:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349509AbiFADyn (ORCPT ); Tue, 31 May 2022 23:54:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232740AbiFADym (ORCPT ); Tue, 31 May 2022 23:54:42 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 017935A090; Tue, 31 May 2022 20:54:41 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 257B560C2D; Wed, 1 Jun 2022 03:54:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EA75EC385B8; Wed, 1 Jun 2022 03:54:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1654055680; bh=Hw0JjLLLLJmJEqRrg3SXTwBDAG1cIOlJGpAbCO5/avU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=MKJ/UpypicQmV5Js/2EpsXg5icbiSKbIoajJ0yHax556P6pZObm2oxOjZsDCB65H+ Vu5wwM1jvXHHdwu/oomCCLR77M8bIfsIh8vx6Y76SC5dpgmM1BGm9AoR4CQnaFBTUJ HpYebHTPPqiXPF6nfDnbdIIQBLjLDQVo678D6CvGZPvu13hWMzn+5lbH0JHk4ECjuF x/+FknlbIGb5mjbC0plI7txLX8jgR4SIOO6StpQagBQSRiQsPwwSaU3u54B2CRUIHm DEdwGeEUErA7PyNTtfRWU84LUEvyqRbGxA0GUAz7mgKp4esS2xX4YwbIZXJeQTBdhc +0MMsfvSkygbg== Date: Tue, 31 May 2022 20:54:38 -0700 From: Jakub Kicinski To: Piyush Malgujar Cc: , , , , , , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Paolo Abeni Subject: Re: [PATCH v2 0/3] net: mdio: mdio-thunder: MDIO clock related changes for Marvell Octeon Family. Message-ID: <20220531205438.4fe7e074@kernel.org> In-Reply-To: <20220530125329.30717-1-pmalgujar@marvell.com> References: <20220530125329.30717-1-pmalgujar@marvell.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, 30 May 2022 05:53:25 -0700 Piyush Malgujar wrote: > This patch series mdio changes are pertaining to Marvell Octeon family. > > 1) clock gating: > The purpose of this change is to apply clock gating for MDIO clock > when there is no transaction happening. This will stop the MDC > clock toggling in idle scenario. > > 2) Marvell MDIO clock frequency attribute change: > This MDIO change provides an option for user to have the bus speed > set to their needs. The clock-freq for Marvell Octeon defaults to > 3.125 MHz and not 2.5 MHz as standard. In case someone needs to use > this attribute, they have to add an extra attribute > "clock-frequency" in the mdio entry in their DTS and this driver > will do the rest. > The changes are made in a way that the clock will set to the > nearest possible value based on the clock calculation and required > frequency from DTS. > > These changes has been verified internally with Marvell Octeon series. Thanks for the patches, this does not sound like a fix tho and we're in the middle of a merge window, so please repost on/after Monday.