From: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
To: <krzysztof.kozlowski+dt@linaro.org>,
<nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<claudiu.beznea@microchip.com>
Cc: <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<kavyasree.kotagiri@microchip.com>,
<UNGLinuxDriver@microchip.com>
Subject: [PATCH v2 2/3] dt-bindings: mfd: atmel,flexcom: Add new compatible string for lan966x
Date: Tue, 7 Jun 2022 20:17:39 +0530 [thread overview]
Message-ID: <20220607144740.14937-3-kavyasree.kotagiri@microchip.com> (raw)
In-Reply-To: <20220607144740.14937-1-kavyasree.kotagiri@microchip.com>
LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1
in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins
can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on
functions being configured.
Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
---
v1 -> v2:
- Use allOf:if:then for lan966x dt properties
.../bindings/mfd/atmel,flexcom.yaml | 39 ++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml
index 05cb6ebb4b2a..2d357217fe22 100644
--- a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml
+++ b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml
@@ -16,7 +16,9 @@ description:
properties:
compatible:
- const: atmel,sama5d2-flexcom
+ enum:
+ - atmel,sama5d2-flexcom
+ - microchip,lan966x-flexcom
reg:
maxItems: 1
@@ -46,6 +48,27 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 3]
+ microchip,flx-shrd-pins:
+ description: Specify the Flexcom shared pins to be used for flexcom
+ chip-selects.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 2
+ items:
+ minimum: 0
+ maximum: 20
+
+ microchip,flx-cs:
+ description: Flexcom chip selects. Here, value of '0' represents "cts" line
+ of flexcom USART or "cs0" line of flexcom SPI and value of '1' represents
+ "rts" line of flexcom USART or "cs1" line of flexcom SPI.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 2
+ items:
+ minimum: 0
+ maximum: 1
+
patternProperties:
"^serial@[0-9a-f]+$":
description: See atmel-usart.txt for details of USART bindings.
@@ -68,6 +91,18 @@ required:
- ranges
- atmel,flexcom-mode
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: microchip,lan966x-flexcom
+
+ then:
+ required:
+ - microchip,flx-shrd-pins
+ - microchip,flx-cs
+
additionalProperties: false
examples:
@@ -80,6 +115,8 @@ examples:
#size-cells = <1>;
ranges = <0x0 0xf8034000 0x800>;
atmel,flexcom-mode = <2>;
+ microchip,flx-shrd-pins = <9>;
+ microchip,flx-cs = <0>;
spi0: spi@400 {
compatible = "atmel,at91rm9200-spi";
--
2.17.1
next prev parent reply other threads:[~2022-06-07 14:48 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-07 14:47 [PATCH v2 0/3] Add support for lan966x flexcom chip-select configuration Kavyasree Kotagiri
2022-06-07 14:47 ` [PATCH v2 1/3] dt-bindings: mfd: atmel,flexcom: Convert to json-schema Kavyasree Kotagiri
2022-06-08 7:25 ` Claudiu.Beznea
2022-06-08 8:34 ` Krzysztof Kozlowski
2022-06-08 9:31 ` Kavyasree.Kotagiri
2022-06-08 9:33 ` Krzysztof Kozlowski
2022-06-16 9:20 ` Kavyasree.Kotagiri
2022-06-16 13:47 ` Krzysztof Kozlowski
2022-06-08 13:45 ` Rob Herring
2022-06-07 14:47 ` Kavyasree Kotagiri [this message]
2022-06-07 14:47 ` [PATCH v2 3/3] mfd: atmel-flexcom: Add support for lan966x flexcom chip-select configuration Kavyasree Kotagiri
2022-06-08 7:35 ` Claudiu.Beznea
2022-06-08 8:20 ` Kavyasree.Kotagiri
2022-06-08 14:17 ` Claudiu.Beznea
2022-06-09 5:18 ` Kavyasree.Kotagiri
2022-06-09 13:34 ` Kavyasree.Kotagiri
2022-06-10 9:06 ` Claudiu.Beznea
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