From: Heiko Stuebner <heiko@sntech.de>
To: palmer@dabbelt.com, paul.walmsley@sifive.com
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
wefu@redhat.com, guoren@kernel.org, cmuellner@linux.com,
philipp.tomsich@vrull.eu, hch@lst.de, samuel@sholland.org,
atishp@atishpatra.org, anup@brainfault.org, mick@ics.forth.gr,
robh+dt@kernel.org, krzk+dt@kernel.org,
devicetree@vger.kernel.org, drew@beagleboard.org,
Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH 1/3] dt-bindings: riscv: document cbom-block-size
Date: Fri, 10 Jun 2022 02:43:06 +0200 [thread overview]
Message-ID: <20220610004308.1903626-2-heiko@sntech.de> (raw)
In-Reply-To: <20220610004308.1903626-1-heiko@sntech.de>
The Zicbom operates on a block-size defined for the cpu-core,
which does not necessarily match other cache-sizes used.
So add the necessary property for the system to know the core's
block-size.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..873dd12f6e89 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -63,6 +63,11 @@ properties:
- riscv,sv48
- riscv,none
+ riscv,cbom-block-size:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The blocksize in bytes for the Zicbom cache operations.
+
riscv,isa:
description:
Identifies the specific RISC-V instruction set architecture
--
2.35.1
next prev parent reply other threads:[~2022-06-10 0:43 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-10 0:43 [PATCH v3 0/3] riscv: implement Zicbom-based CMO instructions + the t-head variant Heiko Stuebner
2022-06-10 0:43 ` Heiko Stuebner [this message]
2022-06-17 20:37 ` [PATCH 1/3] dt-bindings: riscv: document cbom-block-size Rob Herring
2022-06-10 0:43 ` [PATCH 2/3] riscv: Implement Zicbom-based cache management operations Heiko Stuebner
2022-06-10 3:22 ` Randy Dunlap
2022-06-10 5:56 ` Christoph Hellwig
2022-06-15 16:56 ` Heiko Stübner
2022-06-15 17:49 ` Christoph Hellwig
2022-06-16 9:46 ` Heiko Stübner
2022-06-16 11:53 ` Christoph Hellwig
2022-06-16 12:09 ` Heiko Stübner
2022-06-16 12:11 ` Christoph Hellwig
2022-06-17 8:30 ` Heiko Stübner
2022-06-12 19:15 ` Samuel Holland
2022-06-13 5:50 ` Christoph Hellwig
2022-06-10 0:43 ` [PATCH 3/3] riscv: implement cache-management errata for T-Head SoCs Heiko Stuebner
2022-06-10 1:04 ` Guo Ren
2022-06-12 19:18 ` Samuel Holland
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