Re: [PATCH 3/7] PCI: renesas: Add R-Car Gen4 PCIe Host support

[Bjorn Helgaas <helgaas@kernel.org>]

On Mon, Jun 13, 2022 at 08:57:08PM +0900, Yoshihiro Shimoda wrote:
> Add R-Car Gen4 PCIe Host support. This controller is based on
> Synopsys Designware PCIe.

You used "DesignWare" below, which I think is what Synopsys uses.

> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
>  drivers/pci/controller/dwc/Kconfig            |   9 +
>  drivers/pci/controller/dwc/Makefile           |   1 +
>  .../pci/controller/dwc/pcie-rcar-gen4-host.c  | 235 ++++++++++++++++++
>  drivers/pci/controller/dwc/pcie-rcar-gen4.c   | 198 +++++++++++++++
>  drivers/pci/controller/dwc/pcie-rcar-gen4.h   |  59 +++++
>  5 files changed, 502 insertions(+)
>  create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
>  create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c
>  create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.h
> 
> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> index 62ce3abf0f19..3ddccc9c38c5 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -384,4 +384,13 @@ config PCIE_FU740
>  	  Say Y here if you want PCIe controller support for the SiFive
>  	  FU740.
>  
> +config PCIE_RCAR_GEN4
> +	bool "Renesas R-Car Gen4 PCIe Host controller"
> +	depends on ARCH_RENESAS || COMPILE_TEST
> +	depends on PCI_MSI_IRQ_DOMAIN
> +	select PCIE_DW_HOST
> +	help
> +	  Say Y here if you want PCIe host controller support on R-Car Gen4 SoCs.
> +	  This uses the DesignWare core.

> +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
> @@ -0,0 +1,235 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * PCIe host controller driver for Renesas R-Car Gen4 Series SoCs
> + * Copyright (C) 2022 Renesas Electronics Corporation
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/pci.h>
> +#include <linux/platform_device.h>
> +
> +#include "pcie-rcar-gen4.h"
> +#include "pcie-designware.h"
> +
> +/* ASPM L1 PM Substates */
> +#define L1PSCAP(x)		(0x01bc + (x))

Looks like the stuff in pcie-rcar-gen4.h.  Should this go there?

> +	/* Set Max Link Width */

Superfluous comment, since the function name says the same thing.

> +	rcar_gen4_pcie_set_max_link_width(pci, pci->num_lanes);

> +/* Link Capabilities - Maximum Link Width */
> +#define  PCI_EXP_LNKCAP_MLW_X1	BIT(4)
> +#define  PCI_EXP_LNKCAP_MLW_X2	BIT(5)
> +#define  PCI_EXP_LNKCAP_MLW_X4	BIT(6)

I think we should define these in include/uapi/linux/pci_regs.h.
Use the same style as the other #defines there, i.e.,

  #define  PCI_EXP_LNKCAP_MLW_X1  0x00000010
  #define  PCI_EXP_LNKCAP_MLW_X2  0x00000020
  #define  PCI_EXP_LNKCAP_MLW_X4  0x00000040

> +/* Renesas-specific */
> +#define PCIEMSR0		0x0000
> +#define  BIFUR_MOD_SET_ON	(0x1 << 0)
> +#define  DEVICE_TYPE_EP		(0x0 << 2)
> +#define  DEVICE_TYPE_RC		(0x4 << 2)
> +
> +#define PCIEINTSTS0		0x0084
> +#define PCIEINTSTS0EN		0x0310
> +#define  MSI_CTRL_INT		BIT(26)
> +#define  SMLH_LINK_UP		BIT(7)
> +#define  RDLH_LINK_UP		BIT(6)

Is there a reason to mix the "(0x1 << 0)" style and the "BIT(26)"
styles?

> +extern u32 rcar_gen4_pcie_readl(struct rcar_gen4_pcie *pcie, u32 reg);
> +extern void rcar_gen4_pcie_writel(struct rcar_gen4_pcie *pcie, u32 reg, u32 val);
> +extern void rcar_gen4_pcie_set_max_link_width(struct dw_pcie *pci, int num_lanes);
> +extern int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *pcie);
> +extern void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *pcie);
> +extern int rcar_gen4_pcie_pm_runtime_enable(struct device *dev);
> +extern void rcar_gen4_pcie_pm_runtime_disable(struct device *dev);
> +extern int rcar_gen4_pcie_devm_clk_and_reset_get(struct rcar_gen4_pcie *pcie,
> +						 struct device *dev);
> +extern struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct device *dev);

Don't bother with "extern" on function declarations; this would be the
only instance in drivers/pci/.