* [PATCH v5 0/6] SM8350 Display/GPU clock enablement
@ 2022-06-09 9:29 Robert Foss
2022-06-09 9:29 ` [PATCH v5 1/6] arm64: dts: qcom: sm8350: Replace integers with rpmpd defines Robert Foss
` (5 more replies)
0 siblings, 6 replies; 13+ messages in thread
From: Robert Foss @ 2022-06-09 9:29 UTC (permalink / raw)
To: agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt,
robert.foss, jonathan, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Dmitry Baryshkov, Konrad Dybcio
Changes since v2
- Dropped "clk: Introduce CLK_ASSUME_ENABLED_WHEN_UNUSED"
- Dropped "clk: qcom: sm8250-dispcc: Flag shared RCGs as assumed enable"
- Dropped "clk: qcom: rcg2: Cache rate changes for parked RCGs"
Changes sinsce v3:
- Dropped RBs & SoBs for bigger changes
- Changed author to me for patches with big changes
Robert Foss (6):
arm64: dts: qcom: sm8350: Replace integers with rpmpd defines
clk: qcom: add support for SM8350 GPUCC
dt-bindings: clock: Add Qcom SM8350 GPUCC bindings
clk: qcom: add support for SM8350 DISPCC
dt-bindings: clock: Add Qcom SM8350 DISPCC bindings
arm64: dts: qcom: sm8350: Add DISPCC node
.../bindings/clock/qcom,dispcc-sm8350.yaml | 104 ++
.../bindings/clock/qcom,dispcc-sm8x50.yaml | 4 +-
.../bindings/clock/qcom,gpucc-sm8350.yaml | 72 +
arch/arm64/boot/dts/qcom/sm8350.dtsi | 41 +-
drivers/clk/qcom/Kconfig | 17 +
drivers/clk/qcom/Makefile | 2 +
drivers/clk/qcom/dispcc-sm8350.c | 1330 +++++++++++++++++
drivers/clk/qcom/gpucc-sm8350.c | 637 ++++++++
.../dt-bindings/clock/qcom,dispcc-sm8350.h | 1 +
include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 +
10 files changed, 2250 insertions(+), 10 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sm8350.yaml
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml
create mode 100644 drivers/clk/qcom/dispcc-sm8350.c
create mode 100644 drivers/clk/qcom/gpucc-sm8350.c
create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h
create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h
--
2.34.1
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v5 1/6] arm64: dts: qcom: sm8350: Replace integers with rpmpd defines 2022-06-09 9:29 [PATCH v5 0/6] SM8350 Display/GPU clock enablement Robert Foss @ 2022-06-09 9:29 ` Robert Foss 2022-06-09 9:29 ` [PATCH v5 2/6] clk: qcom: add support for SM8350 GPUCC Robert Foss ` (4 subsequent siblings) 5 siblings, 0 replies; 13+ messages in thread From: Robert Foss @ 2022-06-09 9:29 UTC (permalink / raw) To: agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt, robert.foss, jonathan, linux-arm-msm, linux-clk, devicetree, linux-kernel, Dmitry Baryshkov, Konrad Dybcio Replace &rpmhpd power domain integers with their respective defines in order to improve legibility. Signed-off-by: Robert Foss <robert.foss@linaro.org> --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index c0137bdcf94b..52428b6df64e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1656,8 +1656,8 @@ mpss: remoteproc@4080000 { clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd 0>, - <&rpmhpd 12>; + power-domains = <&rpmhpd SM8350_CX>, + <&rpmhpd SM8350_MSS>; power-domain-names = "cx", "mss"; interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; @@ -2167,8 +2167,8 @@ slpi: remoteproc@5c00000 { clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd 4>, - <&rpmhpd 5>; + power-domains = <&rpmhpd SM8350_LCX>, + <&rpmhpd SM8350_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&pil_slpi_mem>; @@ -2235,8 +2235,8 @@ cdsp: remoteproc@98900000 { clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd 0>, - <&rpmhpd 10>; + power-domains = <&rpmhpd SM8350_CX>, + <&rpmhpd SM8350_MXC>; power-domain-names = "cx", "mxc"; interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; @@ -2540,8 +2540,8 @@ adsp: remoteproc@17300000 { clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd 4>, - <&rpmhpd 5>; + power-domains = <&rpmhpd SM8350_LCX>, + <&rpmhpd SM8350_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&pil_adsp_mem>; -- 2.34.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v5 2/6] clk: qcom: add support for SM8350 GPUCC 2022-06-09 9:29 [PATCH v5 0/6] SM8350 Display/GPU clock enablement Robert Foss 2022-06-09 9:29 ` [PATCH v5 1/6] arm64: dts: qcom: sm8350: Replace integers with rpmpd defines Robert Foss @ 2022-06-09 9:29 ` Robert Foss 2022-06-09 10:55 ` Konrad Dybcio 2022-06-09 9:29 ` [PATCH v5 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings Robert Foss ` (3 subsequent siblings) 5 siblings, 1 reply; 13+ messages in thread From: Robert Foss @ 2022-06-09 9:29 UTC (permalink / raw) To: agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt, robert.foss, jonathan, linux-arm-msm, linux-clk, devicetree, linux-kernel, Dmitry Baryshkov, Konrad Dybcio The GPUCC manages the clocks for the Adreno GPU found on the sm8350 SoCs. Signed-off-by: Robert Foss <robert.foss@linaro.org> Signed-off-by: Jonathan Marek <jonathan@marek.ca> --- Changes since v1 - Remove .name assignments for clk_parent_data - Dmitry - Use ARRAY_SIZE where possible - Dmitry - Remove commented out code - Dmitry - Set CLAMP_IO flag for gpu_gx_gdsc - Dmitry - Assign .parent_hws instead of .hw - Dmitry Changes since v2 - Switch license to dual BSD/GPL - Bjorn - Add Jonathans SoB - Jonathan - Add Linaro to copyright statement - Bjorn - Make .hw.init assignment const - Bjorn - Extract & deduplicate bi_tcxo parent_data - Bjorn - Removed further .name assignment - Bjorn - Move of_device_id declaration - Bjorn Changes since v3 - Change license to BSD/GPL - Rob/Bjorn - Switch from .fw_name to .index Changes since v4 - Change year of copyright statement - Change to dual license for header file - Rob drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm8350.c | 637 ++++++++++++++++++++++++++++++++ 3 files changed, 646 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sm8350.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index bc4dcf356d82..b11235c21952 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -712,6 +712,14 @@ config SM_GPUCC_8250 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. +config SM_GPUCC_8350 + tristate "SM8350 Graphics Clock Controller" + select SM_GCC_8350 + help + Support for the graphics clock controller on SM8350 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_VIDEOCC_8150 tristate "SM8150 Video Clock Controller" select SM_GCC_8150 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 36789f5233ef..ef9c64824424 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -101,6 +101,7 @@ obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o +obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm8350.c new file mode 100644 index 000000000000..68d85757e064 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm8350.c @@ -0,0 +1,637 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,gpucc-sm8350.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-divider.h" +#include "gdsc.h" +#include "reset.h" + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static struct pll_vco lucid_5lpe_vco[] = { + { 249600000, 1750000000, 0 }, +}; + +static const struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x18, + .alpha = 0x6000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x2A9A699C, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000000, + .test_ctl_hi1_val = 0x01800000, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static const struct clk_parent_data gpu_cc_parent = { + .fw_name = "bi_tcxo", +}; + +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .vco_table = lucid_5lpe_vco, + .num_vco = ARRAY_SIZE(lucid_5lpe_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_pll0", + .parent_data = &gpu_cc_parent, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_5lpe_ops, + }, + }, +}; + +static const struct alpha_pll_config gpu_cc_pll1_config = { + .l = 0x1A, + .alpha = 0xAAA, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x2A9A699C, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000000, + .test_ctl_hi1_val = 0x01800000, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll gpu_cc_pll1 = { + .offset = 0x100, + .vco_table = lucid_5lpe_vco, + .num_vco = ARRAY_SIZE(lucid_5lpe_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll1", + .parent_data = &gpu_cc_parent, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_5lpe_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + gpu_cc_parent, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .fw_name = "gcc_gpu_gpll0_clk_src" }, + { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + gpu_cc_parent, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .fw_name = "gcc_gpu_gpll0_clk_src" }, + { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), + F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { + F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src = { + .cmd_rcgr = 0x117c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_hub_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hub_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = { + .reg = 0x11c0, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gpu_cc_hub_ahb_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = { + .reg = 0x11bc, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gpu_cc_hub_cx_int_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x1078, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cb_clk = { + .halt_reg = 0x1170, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1170, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x107c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x107c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_apb_clk = { + .halt_reg = 0x1088, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1088, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_apb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_qdss_at_clk = { + .halt_reg = 0x1080, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1080, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_qdss_at_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_qdss_trig_clk = { + .halt_reg = 0x1094, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1094, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_qdss_trig_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = { + .halt_reg = 0x1084, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1084, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_qdss_tsctr_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x1004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_freq_measure_clk = { + .halt_reg = 0x120c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x120c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_freq_measure_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gmu_clk = { + .halt_reg = 0x1064, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1064, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gmu_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = { + .halt_reg = 0x105c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x105c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_qdss_tsctr_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_vsense_clk = { + .halt_reg = 0x1058, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_vsense_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x5000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk = { + .halt_reg = 0x1178, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1178, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hub_aon_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk = { + .halt_reg = 0x1204, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1204, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hub_cx_int_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = { + .halt_reg = 0x802c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x802c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_mnd1x_0_gfx3d_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = { + .halt_reg = 0x8030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_mnd1x_1_gfx3d_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x1090, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc = { + .gdscr = 0x106c, + .gds_hw_ctrl = 0x1540, + .pd = { + .name = "gpu_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc gpu_gx_gdsc = { + .gdscr = 0x100c, + .clamp_io_ctrl = 0x1508, + .pd = { + .name = "gpu_gx_gdsc", + .power_on = gdsc_gx_do_nothing_enable, + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR, +}; + +static struct clk_regmap *gpu_cc_sm8350_clocks[] = { + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_QDSS_AT_CLK] = &gpu_cc_cx_qdss_at_clk.clkr, + [GPU_CC_CX_QDSS_TRIG_CLK] = &gpu_cc_cx_qdss_trig_clk.clkr, + [GPU_CC_CX_QDSS_TSCTR_CLK] = &gpu_cc_cx_qdss_tsctr_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, + [GPU_CC_GX_QDSS_TSCTR_CLK] = &gpu_cc_gx_qdss_tsctr_clk.clkr, + [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr, + [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr, + [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr, + [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, +}; + +static const struct qcom_reset_map gpu_cc_sm8350_resets[] = { + [GPUCC_GPU_CC_ACD_BCR] = { 0x1160 }, + [GPUCC_GPU_CC_CB_BCR] = { 0x116c }, + [GPUCC_GPU_CC_CX_BCR] = { 0x1068 }, + [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x1174 }, + [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 }, + [GPUCC_GPU_CC_GMU_BCR] = { 0x111c }, + [GPUCC_GPU_CC_GX_BCR] = { 0x1008 }, + [GPUCC_GPU_CC_XO_BCR] = { 0x1000 }, +}; + +static struct gdsc *gpu_cc_sm8350_gdscs[] = { + [GPU_CX_GDSC] = &gpu_cx_gdsc, + [GPU_GX_GDSC] = &gpu_gx_gdsc, +}; + +static const struct regmap_config gpu_cc_sm8350_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x8030, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_sm8350_desc = { + .config = &gpu_cc_sm8350_regmap_config, + .clks = gpu_cc_sm8350_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sm8350_clocks), + .resets = gpu_cc_sm8350_resets, + .num_resets = ARRAY_SIZE(gpu_cc_sm8350_resets), + .gdscs = gpu_cc_sm8350_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_sm8350_gdscs), +}; + +static int gpu_cc_sm8350_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gpu_cc_sm8350_desc); + if (IS_ERR(regmap)) { + dev_err(&pdev->dev, "Failed to map gpu cc registers\n"); + return PTR_ERR(regmap); + } + + clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + + return qcom_cc_really_probe(pdev, &gpu_cc_sm8350_desc, regmap); +} + +static const struct of_device_id gpu_cc_sm8350_match_table[] = { + { .compatible = "qcom,sm8350-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm8350_match_table); + +static struct platform_driver gpu_cc_sm8350_driver = { + .probe = gpu_cc_sm8350_probe, + .driver = { + .name = "sm8350-gpucc", + .of_match_table = gpu_cc_sm8350_match_table, + }, +}; + +static int __init gpu_cc_sm8350_init(void) +{ + return platform_driver_register(&gpu_cc_sm8350_driver); +} +subsys_initcall(gpu_cc_sm8350_init); + +static void __exit gpu_cc_sm8350_exit(void) +{ + platform_driver_unregister(&gpu_cc_sm8350_driver); +} +module_exit(gpu_cc_sm8350_exit); + +MODULE_DESCRIPTION("QTI GPU_CC SM8350 Driver"); +MODULE_LICENSE("GPL v2"); -- 2.34.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v5 2/6] clk: qcom: add support for SM8350 GPUCC 2022-06-09 9:29 ` [PATCH v5 2/6] clk: qcom: add support for SM8350 GPUCC Robert Foss @ 2022-06-09 10:55 ` Konrad Dybcio 2022-06-09 11:56 ` Robert Foss 0 siblings, 1 reply; 13+ messages in thread From: Konrad Dybcio @ 2022-06-09 10:55 UTC (permalink / raw) To: Robert Foss, agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt, jonathan, linux-arm-msm, linux-clk, devicetree, linux-kernel, Dmitry Baryshkov On 09/06/2022 11:29, Robert Foss wrote: > The GPUCC manages the clocks for the Adreno GPU found on the > sm8350 SoCs. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > Signed-off-by: Jonathan Marek <jonathan@marek.ca> > --- > > Changes since v1 > - Remove .name assignments for clk_parent_data - Dmitry > - Use ARRAY_SIZE where possible - Dmitry > - Remove commented out code - Dmitry > - Set CLAMP_IO flag for gpu_gx_gdsc - Dmitry > - Assign .parent_hws instead of .hw - Dmitry > > Changes since v2 > - Switch license to dual BSD/GPL - Bjorn > - Add Jonathans SoB - Jonathan > - Add Linaro to copyright statement - Bjorn > - Make .hw.init assignment const - Bjorn > - Extract & deduplicate bi_tcxo parent_data - Bjorn > - Removed further .name assignment - Bjorn > - Move of_device_id declaration - Bjorn > > Changes since v3 > - Change license to BSD/GPL - Rob/Bjorn > - Switch from .fw_name to .index > > Changes since v4 > - Change year of copyright statement > - Change to dual license for header file - Rob > > > drivers/clk/qcom/Kconfig | 8 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/gpucc-sm8350.c | 637 ++++++++++++++++++++++++++++++++ > 3 files changed, 646 insertions(+) > create mode 100644 drivers/clk/qcom/gpucc-sm8350.c > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index bc4dcf356d82..b11235c21952 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -712,6 +712,14 @@ config SM_GPUCC_8250 > Say Y if you want to support graphics controller devices and > functionality such as 3D graphics. > > +config SM_GPUCC_8350 > + tristate "SM8350 Graphics Clock Controller" > + select SM_GCC_8350 > + help > + Support for the graphics clock controller on SM8350 devices. > + Say Y if you want to support graphics controller devices and > + functionality such as 3D graphics. > + > config SM_VIDEOCC_8150 > tristate "SM8150 Video Clock Controller" > select SM_GCC_8150 > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index 36789f5233ef..ef9c64824424 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -101,6 +101,7 @@ obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o > obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o > obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o > obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o > +obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o > obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o > obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o > obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o > diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm8350.c > new file mode 100644 > index 000000000000..68d85757e064 > --- /dev/null > +++ b/drivers/clk/qcom/gpucc-sm8350.c > @@ -0,0 +1,637 @@ > +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause > +/* > + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. > + * Copyright (c) 2022, Linaro Limited > + */ > + > +#include <linux/clk.h> > +#include <linux/err.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of_device.h> > +#include <linux/of.h> > +#include <linux/regmap.h> > + > +#include <dt-bindings/clock/qcom,gpucc-sm8350.h> > + > +#include "clk-alpha-pll.h" > +#include "clk-branch.h" > +#include "clk-pll.h" > +#include "clk-rcg.h" > +#include "clk-regmap.h" > +#include "common.h" > +#include "clk-regmap-mux.h" > +#include "clk-regmap-divider.h" > +#include "gdsc.h" > +#include "reset.h" > + > +enum { > + P_BI_TCXO, > + P_GPLL0_OUT_MAIN, > + P_GPLL0_OUT_MAIN_DIV, > + P_GPU_CC_PLL0_OUT_MAIN, > + P_GPU_CC_PLL1_OUT_MAIN, > +}; > + > +static struct pll_vco lucid_5lpe_vco[] = { > + { 249600000, 1750000000, 0 }, > +}; > + > +static const struct alpha_pll_config gpu_cc_pll0_config = { > + .l = 0x18, > + .alpha = 0x6000, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00002261, > + .config_ctl_hi1_val = 0x2A9A699C, Lowercase hex, please. > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000000, > + .test_ctl_hi1_val = 0x01800000, > + .user_ctl_val = 0x00000000, > + .user_ctl_hi_val = 0x00000805, > + .user_ctl_hi1_val = 0x00000000, > +}; > + > +static const struct clk_parent_data gpu_cc_parent = { > + .fw_name = "bi_tcxo", > +}; > + > +static struct clk_alpha_pll gpu_cc_pll0 = { > + .offset = 0x0, > + .vco_table = lucid_5lpe_vco, > + .num_vco = ARRAY_SIZE(lucid_5lpe_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > + .clkr = { > + .hw.init = &(const struct clk_init_data){ > + .name = "gpu_cc_pll0", > + .parent_data = &gpu_cc_parent, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_5lpe_ops, > + }, > + }, > +}; > + > +static const struct alpha_pll_config gpu_cc_pll1_config = { > + .l = 0x1A, > + .alpha = 0xAAA, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00002261, > + .config_ctl_hi1_val = 0x2A9A699C, > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000000, > + .test_ctl_hi1_val = 0x01800000, > + .user_ctl_val = 0x00000000, > + .user_ctl_hi_val = 0x00000805, > + .user_ctl_hi1_val = 0x00000000, > +}; > + > +static struct clk_alpha_pll gpu_cc_pll1 = { > + .offset = 0x100, > + .vco_table = lucid_5lpe_vco, > + .num_vco = ARRAY_SIZE(lucid_5lpe_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > + .clkr = { > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_pll1", > + .parent_data = &gpu_cc_parent, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_5lpe_ops, > + }, > + }, > +}; > + > +static const struct parent_map gpu_cc_parent_map_0[] = { > + { P_BI_TCXO, 0 }, > + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, > + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, > + { P_GPLL0_OUT_MAIN, 5 }, > + { P_GPLL0_OUT_MAIN_DIV, 6 }, > +}; > + > +static const struct clk_parent_data gpu_cc_parent_data_0[] = { > + gpu_cc_parent, > + { .hw = &gpu_cc_pll0.clkr.hw }, > + { .hw = &gpu_cc_pll1.clkr.hw }, > + { .fw_name = "gcc_gpu_gpll0_clk_src" }, > + { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, > +}; > + > +static const struct parent_map gpu_cc_parent_map_1[] = { > + { P_BI_TCXO, 0 }, > + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, > + { P_GPLL0_OUT_MAIN, 5 }, > + { P_GPLL0_OUT_MAIN_DIV, 6 }, > +}; > + > +static const struct clk_parent_data gpu_cc_parent_data_1[] = { > + gpu_cc_parent, > + { .hw = &gpu_cc_pll1.clkr.hw }, > + { .fw_name = "gcc_gpu_gpll0_clk_src" }, > + { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, > +}; > + > +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), > + F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gpu_cc_gmu_clk_src = { > + .cmd_rcgr = 0x1120, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gpu_cc_parent_map_0, > + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_gmu_clk_src", > + .parent_data = gpu_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { > + F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), > + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), > + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gpu_cc_hub_clk_src = { > + .cmd_rcgr = 0x117c, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gpu_cc_parent_map_1, > + .freq_tbl = ftbl_gpu_cc_hub_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_hub_clk_src", > + .parent_data = gpu_cc_parent_data_1, > + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = { > + .reg = 0x11c0, > + .shift = 0, > + .width = 4, > + .clkr.hw.init = &(struct clk_init_data) { > + .name = "gpu_cc_hub_ahb_div_clk_src", > + .parent_hws = (const struct clk_hw*[]){ > + &gpu_cc_hub_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_regmap_div_ro_ops, > + }, > +}; > + > +static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = { > + .reg = 0x11bc, > + .shift = 0, > + .width = 4, > + .clkr.hw.init = &(struct clk_init_data) { > + .name = "gpu_cc_hub_cx_int_div_clk_src", > + .parent_hws = (const struct clk_hw*[]){ > + &gpu_cc_hub_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_regmap_div_ro_ops, > + }, > +}; > + > +static struct clk_branch gpu_cc_ahb_clk = { > + .halt_reg = 0x1078, > + .halt_check = BRANCH_HALT_DELAY, > + .clkr = { > + .enable_reg = 0x1078, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_ahb_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_cb_clk = { > + .halt_reg = 0x1170, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1170, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_cb_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_crc_ahb_clk = { > + .halt_reg = 0x107c, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x107c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_crc_ahb_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_cx_apb_clk = { > + .halt_reg = 0x1088, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x1088, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_cx_apb_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_cx_gmu_clk = { > + .halt_reg = 0x1098, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1098, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_cx_gmu_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &gpu_cc_gmu_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_aon_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_cx_qdss_at_clk = { > + .halt_reg = 0x1080, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x1080, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_cx_qdss_at_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_cx_qdss_trig_clk = { > + .halt_reg = 0x1094, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x1094, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_cx_qdss_trig_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = { > + .halt_reg = 0x1084, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x1084, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_cx_qdss_tsctr_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { > + .halt_reg = 0x108c, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x108c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_cx_snoc_dvm_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_cxo_aon_clk = { > + .halt_reg = 0x1004, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x1004, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_cxo_aon_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_cxo_clk = { > + .halt_reg = 0x109c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x109c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_cxo_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_freq_measure_clk = { > + .halt_reg = 0x120c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x120c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_freq_measure_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_gx_gmu_clk = { > + .halt_reg = 0x1064, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1064, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_gx_gmu_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &gpu_cc_gmu_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = { > + .halt_reg = 0x105c, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x105c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_gx_qdss_tsctr_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_gx_vsense_clk = { > + .halt_reg = 0x1058, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x1058, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_gx_vsense_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { > + .halt_reg = 0x5000, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x5000, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_hub_aon_clk = { > + .halt_reg = 0x1178, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1178, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_hub_aon_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &gpu_cc_hub_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_aon_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_hub_cx_int_clk = { > + .halt_reg = 0x1204, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1204, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_hub_cx_int_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_aon_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = { > + .halt_reg = 0x802c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x802c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_mnd1x_0_gfx3d_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = { > + .halt_reg = 0x8030, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x8030, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_mnd1x_1_gfx3d_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_sleep_clk = { > + .halt_reg = 0x1090, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x1090, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_sleep_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct gdsc gpu_cx_gdsc = { > + .gdscr = 0x106c, > + .gds_hw_ctrl = 0x1540, > + .pd = { > + .name = "gpu_cx_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = VOTABLE, > +}; > + > +static struct gdsc gpu_gx_gdsc = { > + .gdscr = 0x100c, > + .clamp_io_ctrl = 0x1508, > + .pd = { > + .name = "gpu_gx_gdsc", > + .power_on = gdsc_gx_do_nothing_enable, > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR, > +}; > + > +static struct clk_regmap *gpu_cc_sm8350_clocks[] = { > + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, > + [GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr, > + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, > + [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, > + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, > + [GPU_CC_CX_QDSS_AT_CLK] = &gpu_cc_cx_qdss_at_clk.clkr, > + [GPU_CC_CX_QDSS_TRIG_CLK] = &gpu_cc_cx_qdss_trig_clk.clkr, > + [GPU_CC_CX_QDSS_TSCTR_CLK] = &gpu_cc_cx_qdss_tsctr_clk.clkr, > + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, > + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, > + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, > + [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, > + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, > + [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, > + [GPU_CC_GX_QDSS_TSCTR_CLK] = &gpu_cc_gx_qdss_tsctr_clk.clkr, > + [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr, > + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, > + [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr, > + [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, > + [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, > + [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, > + [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr, > + [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr, > + [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr, > + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, > + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, > + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, > +}; > + > +static const struct qcom_reset_map gpu_cc_sm8350_resets[] = { > + [GPUCC_GPU_CC_ACD_BCR] = { 0x1160 }, > + [GPUCC_GPU_CC_CB_BCR] = { 0x116c }, > + [GPUCC_GPU_CC_CX_BCR] = { 0x1068 }, > + [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x1174 }, > + [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 }, > + [GPUCC_GPU_CC_GMU_BCR] = { 0x111c }, > + [GPUCC_GPU_CC_GX_BCR] = { 0x1008 }, > + [GPUCC_GPU_CC_XO_BCR] = { 0x1000 }, > +}; > + > +static struct gdsc *gpu_cc_sm8350_gdscs[] = { > + [GPU_CX_GDSC] = &gpu_cx_gdsc, > + [GPU_GX_GDSC] = &gpu_gx_gdsc, > +}; > + > +static const struct regmap_config gpu_cc_sm8350_regmap_config = { > + .reg_bits = 32, > + .reg_stride = 4, > + .val_bits = 32, > + .max_register = 0x8030, > + .fast_io = true, > +}; > + > +static const struct qcom_cc_desc gpu_cc_sm8350_desc = { > + .config = &gpu_cc_sm8350_regmap_config, > + .clks = gpu_cc_sm8350_clocks, > + .num_clks = ARRAY_SIZE(gpu_cc_sm8350_clocks), > + .resets = gpu_cc_sm8350_resets, > + .num_resets = ARRAY_SIZE(gpu_cc_sm8350_resets), > + .gdscs = gpu_cc_sm8350_gdscs, > + .num_gdscs = ARRAY_SIZE(gpu_cc_sm8350_gdscs), > +}; > + > +static int gpu_cc_sm8350_probe(struct platform_device *pdev) > +{ > + struct regmap *regmap; > + > + regmap = qcom_cc_map(pdev, &gpu_cc_sm8350_desc); > + if (IS_ERR(regmap)) { > + dev_err(&pdev->dev, "Failed to map gpu cc registers\n"); I think we'd get a probe error even without this, no? Konrad > + return PTR_ERR(regmap); > + } > + > + clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); > + clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); > + > + return qcom_cc_really_probe(pdev, &gpu_cc_sm8350_desc, regmap); > +} > + > +static const struct of_device_id gpu_cc_sm8350_match_table[] = { > + { .compatible = "qcom,sm8350-gpucc" }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, gpu_cc_sm8350_match_table); > + > +static struct platform_driver gpu_cc_sm8350_driver = { > + .probe = gpu_cc_sm8350_probe, > + .driver = { > + .name = "sm8350-gpucc", > + .of_match_table = gpu_cc_sm8350_match_table, > + }, > +}; > + > +static int __init gpu_cc_sm8350_init(void) > +{ > + return platform_driver_register(&gpu_cc_sm8350_driver); > +} > +subsys_initcall(gpu_cc_sm8350_init); > + > +static void __exit gpu_cc_sm8350_exit(void) > +{ > + platform_driver_unregister(&gpu_cc_sm8350_driver); > +} > +module_exit(gpu_cc_sm8350_exit); > + > +MODULE_DESCRIPTION("QTI GPU_CC SM8350 Driver"); > +MODULE_LICENSE("GPL v2"); ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5 2/6] clk: qcom: add support for SM8350 GPUCC 2022-06-09 10:55 ` Konrad Dybcio @ 2022-06-09 11:56 ` Robert Foss 0 siblings, 0 replies; 13+ messages in thread From: Robert Foss @ 2022-06-09 11:56 UTC (permalink / raw) To: Konrad Dybcio Cc: agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt, jonathan, linux-arm-msm, linux-clk, devicetree, linux-kernel, Dmitry Baryshkov On Thu, 9 Jun 2022 at 12:55, Konrad Dybcio <konrad.dybcio@somainline.org> wrote: > > > On 09/06/2022 11:29, Robert Foss wrote: > > The GPUCC manages the clocks for the Adreno GPU found on the > > sm8350 SoCs. > > > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > > Signed-off-by: Jonathan Marek <jonathan@marek.ca> > > --- > > > > Changes since v1 > > - Remove .name assignments for clk_parent_data - Dmitry > > - Use ARRAY_SIZE where possible - Dmitry > > - Remove commented out code - Dmitry > > - Set CLAMP_IO flag for gpu_gx_gdsc - Dmitry > > - Assign .parent_hws instead of .hw - Dmitry > > > > Changes since v2 > > - Switch license to dual BSD/GPL - Bjorn > > - Add Jonathans SoB - Jonathan > > - Add Linaro to copyright statement - Bjorn > > - Make .hw.init assignment const - Bjorn > > - Extract & deduplicate bi_tcxo parent_data - Bjorn > > - Removed further .name assignment - Bjorn > > - Move of_device_id declaration - Bjorn > > > > Changes since v3 > > - Change license to BSD/GPL - Rob/Bjorn > > - Switch from .fw_name to .index > > > > Changes since v4 > > - Change year of copyright statement > > - Change to dual license for header file - Rob > > > > > > drivers/clk/qcom/Kconfig | 8 + > > drivers/clk/qcom/Makefile | 1 + > > drivers/clk/qcom/gpucc-sm8350.c | 637 ++++++++++++++++++++++++++++++++ > > 3 files changed, 646 insertions(+) > > create mode 100644 drivers/clk/qcom/gpucc-sm8350.c > > > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > > index bc4dcf356d82..b11235c21952 100644 > > --- a/drivers/clk/qcom/Kconfig > > +++ b/drivers/clk/qcom/Kconfig > > @@ -712,6 +712,14 @@ config SM_GPUCC_8250 > > Say Y if you want to support graphics controller devices and > > functionality such as 3D graphics. > > > > +config SM_GPUCC_8350 > > + tristate "SM8350 Graphics Clock Controller" > > + select SM_GCC_8350 > > + help > > + Support for the graphics clock controller on SM8350 devices. > > + Say Y if you want to support graphics controller devices and > > + functionality such as 3D graphics. > > + > > config SM_VIDEOCC_8150 > > tristate "SM8150 Video Clock Controller" > > select SM_GCC_8150 > > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > > index 36789f5233ef..ef9c64824424 100644 > > --- a/drivers/clk/qcom/Makefile > > +++ b/drivers/clk/qcom/Makefile > > @@ -101,6 +101,7 @@ obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o > > obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o > > obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o > > obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o > > +obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o > > obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o > > obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o > > obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o > > diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm8350.c > > new file mode 100644 > > index 000000000000..68d85757e064 > > --- /dev/null > > +++ b/drivers/clk/qcom/gpucc-sm8350.c > > @@ -0,0 +1,637 @@ > > +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause > > +/* > > + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. > > + * Copyright (c) 2022, Linaro Limited > > + */ > > + > > +#include <linux/clk.h> > > +#include <linux/err.h> > > +#include <linux/kernel.h> > > +#include <linux/module.h> > > +#include <linux/of_device.h> > > +#include <linux/of.h> > > +#include <linux/regmap.h> > > + > > +#include <dt-bindings/clock/qcom,gpucc-sm8350.h> > > + > > +#include "clk-alpha-pll.h" > > +#include "clk-branch.h" > > +#include "clk-pll.h" > > +#include "clk-rcg.h" > > +#include "clk-regmap.h" > > +#include "common.h" > > +#include "clk-regmap-mux.h" > > +#include "clk-regmap-divider.h" > > +#include "gdsc.h" > > +#include "reset.h" > > + > > +enum { > > + P_BI_TCXO, > > + P_GPLL0_OUT_MAIN, > > + P_GPLL0_OUT_MAIN_DIV, > > + P_GPU_CC_PLL0_OUT_MAIN, > > + P_GPU_CC_PLL1_OUT_MAIN, > > +}; > > + > > +static struct pll_vco lucid_5lpe_vco[] = { > > + { 249600000, 1750000000, 0 }, > > +}; > > + > > +static const struct alpha_pll_config gpu_cc_pll0_config = { > > + .l = 0x18, > > + .alpha = 0x6000, > > + .config_ctl_val = 0x20485699, > > + .config_ctl_hi_val = 0x00002261, > > + .config_ctl_hi1_val = 0x2A9A699C, > > Lowercase hex, please. Ack. > > > > + .test_ctl_val = 0x00000000, > > + .test_ctl_hi_val = 0x00000000, > > + .test_ctl_hi1_val = 0x01800000, > > + .user_ctl_val = 0x00000000, > > + .user_ctl_hi_val = 0x00000805, > > + .user_ctl_hi1_val = 0x00000000, > > +}; > > + > > +static const struct clk_parent_data gpu_cc_parent = { > > + .fw_name = "bi_tcxo", > > +}; > > + > > +static struct clk_alpha_pll gpu_cc_pll0 = { > > + .offset = 0x0, > > + .vco_table = lucid_5lpe_vco, > > + .num_vco = ARRAY_SIZE(lucid_5lpe_vco), > > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > > + .clkr = { > > + .hw.init = &(const struct clk_init_data){ > > + .name = "gpu_cc_pll0", > > + .parent_data = &gpu_cc_parent, > > + .num_parents = 1, > > + .ops = &clk_alpha_pll_lucid_5lpe_ops, > > + }, > > + }, > > +}; > > + > > +static const struct alpha_pll_config gpu_cc_pll1_config = { > > + .l = 0x1A, > > + .alpha = 0xAAA, > > + .config_ctl_val = 0x20485699, > > + .config_ctl_hi_val = 0x00002261, > > + .config_ctl_hi1_val = 0x2A9A699C, > > + .test_ctl_val = 0x00000000, > > + .test_ctl_hi_val = 0x00000000, > > + .test_ctl_hi1_val = 0x01800000, > > + .user_ctl_val = 0x00000000, > > + .user_ctl_hi_val = 0x00000805, > > + .user_ctl_hi1_val = 0x00000000, > > +}; > > + > > +static struct clk_alpha_pll gpu_cc_pll1 = { > > + .offset = 0x100, > > + .vco_table = lucid_5lpe_vco, > > + .num_vco = ARRAY_SIZE(lucid_5lpe_vco), > > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > > + .clkr = { > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_pll1", > > + .parent_data = &gpu_cc_parent, > > + .num_parents = 1, > > + .ops = &clk_alpha_pll_lucid_5lpe_ops, > > + }, > > + }, > > +}; > > + > > +static const struct parent_map gpu_cc_parent_map_0[] = { > > + { P_BI_TCXO, 0 }, > > + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, > > + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, > > + { P_GPLL0_OUT_MAIN, 5 }, > > + { P_GPLL0_OUT_MAIN_DIV, 6 }, > > +}; > > + > > +static const struct clk_parent_data gpu_cc_parent_data_0[] = { > > + gpu_cc_parent, > > + { .hw = &gpu_cc_pll0.clkr.hw }, > > + { .hw = &gpu_cc_pll1.clkr.hw }, > > + { .fw_name = "gcc_gpu_gpll0_clk_src" }, > > + { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, > > +}; > > + > > +static const struct parent_map gpu_cc_parent_map_1[] = { > > + { P_BI_TCXO, 0 }, > > + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, > > + { P_GPLL0_OUT_MAIN, 5 }, > > + { P_GPLL0_OUT_MAIN_DIV, 6 }, > > +}; > > + > > +static const struct clk_parent_data gpu_cc_parent_data_1[] = { > > + gpu_cc_parent, > > + { .hw = &gpu_cc_pll1.clkr.hw }, > > + { .fw_name = "gcc_gpu_gpll0_clk_src" }, > > + { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, > > +}; > > + > > +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { > > + F(19200000, P_BI_TCXO, 1, 0, 0), > > + F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), > > + F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0), > > + { } > > +}; > > + > > +static struct clk_rcg2 gpu_cc_gmu_clk_src = { > > + .cmd_rcgr = 0x1120, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = gpu_cc_parent_map_0, > > + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_gmu_clk_src", > > + .parent_data = gpu_cc_parent_data_0, > > + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_rcg2_ops, > > + }, > > +}; > > + > > +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { > > + F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), > > + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), > > + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), > > + { } > > +}; > > + > > +static struct clk_rcg2 gpu_cc_hub_clk_src = { > > + .cmd_rcgr = 0x117c, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = gpu_cc_parent_map_1, > > + .freq_tbl = ftbl_gpu_cc_hub_clk_src, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_hub_clk_src", > > + .parent_data = gpu_cc_parent_data_1, > > + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_rcg2_ops, > > + }, > > +}; > > + > > +static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = { > > + .reg = 0x11c0, > > + .shift = 0, > > + .width = 4, > > + .clkr.hw.init = &(struct clk_init_data) { > > + .name = "gpu_cc_hub_ahb_div_clk_src", > > + .parent_hws = (const struct clk_hw*[]){ > > + &gpu_cc_hub_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_regmap_div_ro_ops, > > + }, > > +}; > > + > > +static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = { > > + .reg = 0x11bc, > > + .shift = 0, > > + .width = 4, > > + .clkr.hw.init = &(struct clk_init_data) { > > + .name = "gpu_cc_hub_cx_int_div_clk_src", > > + .parent_hws = (const struct clk_hw*[]){ > > + &gpu_cc_hub_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_regmap_div_ro_ops, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_ahb_clk = { > > + .halt_reg = 0x1078, > > + .halt_check = BRANCH_HALT_DELAY, > > + .clkr = { > > + .enable_reg = 0x1078, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_ahb_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_cb_clk = { > > + .halt_reg = 0x1170, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x1170, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_cb_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_crc_ahb_clk = { > > + .halt_reg = 0x107c, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x107c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_crc_ahb_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_cx_apb_clk = { > > + .halt_reg = 0x1088, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x1088, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_cx_apb_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_cx_gmu_clk = { > > + .halt_reg = 0x1098, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x1098, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_cx_gmu_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &gpu_cc_gmu_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_aon_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_cx_qdss_at_clk = { > > + .halt_reg = 0x1080, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x1080, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_cx_qdss_at_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_cx_qdss_trig_clk = { > > + .halt_reg = 0x1094, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x1094, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_cx_qdss_trig_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = { > > + .halt_reg = 0x1084, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x1084, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_cx_qdss_tsctr_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { > > + .halt_reg = 0x108c, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x108c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_cx_snoc_dvm_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_cxo_aon_clk = { > > + .halt_reg = 0x1004, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x1004, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_cxo_aon_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_cxo_clk = { > > + .halt_reg = 0x109c, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x109c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_cxo_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_freq_measure_clk = { > > + .halt_reg = 0x120c, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x120c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_freq_measure_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_gx_gmu_clk = { > > + .halt_reg = 0x1064, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x1064, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_gx_gmu_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &gpu_cc_gmu_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = { > > + .halt_reg = 0x105c, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x105c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_gx_qdss_tsctr_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_gx_vsense_clk = { > > + .halt_reg = 0x1058, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x1058, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_gx_vsense_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { > > + .halt_reg = 0x5000, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x5000, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_hub_aon_clk = { > > + .halt_reg = 0x1178, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x1178, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_hub_aon_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &gpu_cc_hub_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_aon_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_hub_cx_int_clk = { > > + .halt_reg = 0x1204, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x1204, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_hub_cx_int_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_aon_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = { > > + .halt_reg = 0x802c, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x802c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_mnd1x_0_gfx3d_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = { > > + .halt_reg = 0x8030, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x8030, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_mnd1x_1_gfx3d_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_sleep_clk = { > > + .halt_reg = 0x1090, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x1090, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_sleep_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct gdsc gpu_cx_gdsc = { > > + .gdscr = 0x106c, > > + .gds_hw_ctrl = 0x1540, > > + .pd = { > > + .name = "gpu_cx_gdsc", > > + }, > > + .pwrsts = PWRSTS_OFF_ON, > > + .flags = VOTABLE, > > +}; > > + > > +static struct gdsc gpu_gx_gdsc = { > > + .gdscr = 0x100c, > > + .clamp_io_ctrl = 0x1508, > > + .pd = { > > + .name = "gpu_gx_gdsc", > > + .power_on = gdsc_gx_do_nothing_enable, > > + }, > > + .pwrsts = PWRSTS_OFF_ON, > > + .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR, > > +}; > > + > > +static struct clk_regmap *gpu_cc_sm8350_clocks[] = { > > + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, > > + [GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr, > > + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, > > + [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, > > + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, > > + [GPU_CC_CX_QDSS_AT_CLK] = &gpu_cc_cx_qdss_at_clk.clkr, > > + [GPU_CC_CX_QDSS_TRIG_CLK] = &gpu_cc_cx_qdss_trig_clk.clkr, > > + [GPU_CC_CX_QDSS_TSCTR_CLK] = &gpu_cc_cx_qdss_tsctr_clk.clkr, > > + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, > > + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, > > + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, > > + [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, > > + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, > > + [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, > > + [GPU_CC_GX_QDSS_TSCTR_CLK] = &gpu_cc_gx_qdss_tsctr_clk.clkr, > > + [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr, > > + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, > > + [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr, > > + [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, > > + [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, > > + [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, > > + [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr, > > + [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr, > > + [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr, > > + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, > > + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, > > + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, > > +}; > > + > > +static const struct qcom_reset_map gpu_cc_sm8350_resets[] = { > > + [GPUCC_GPU_CC_ACD_BCR] = { 0x1160 }, > > + [GPUCC_GPU_CC_CB_BCR] = { 0x116c }, > > + [GPUCC_GPU_CC_CX_BCR] = { 0x1068 }, > > + [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x1174 }, > > + [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 }, > > + [GPUCC_GPU_CC_GMU_BCR] = { 0x111c }, > > + [GPUCC_GPU_CC_GX_BCR] = { 0x1008 }, > > + [GPUCC_GPU_CC_XO_BCR] = { 0x1000 }, > > +}; > > + > > +static struct gdsc *gpu_cc_sm8350_gdscs[] = { > > + [GPU_CX_GDSC] = &gpu_cx_gdsc, > > + [GPU_GX_GDSC] = &gpu_gx_gdsc, > > +}; > > + > > +static const struct regmap_config gpu_cc_sm8350_regmap_config = { > > + .reg_bits = 32, > > + .reg_stride = 4, > > + .val_bits = 32, > > + .max_register = 0x8030, > > + .fast_io = true, > > +}; > > + > > +static const struct qcom_cc_desc gpu_cc_sm8350_desc = { > > + .config = &gpu_cc_sm8350_regmap_config, > > + .clks = gpu_cc_sm8350_clocks, > > + .num_clks = ARRAY_SIZE(gpu_cc_sm8350_clocks), > > + .resets = gpu_cc_sm8350_resets, > > + .num_resets = ARRAY_SIZE(gpu_cc_sm8350_resets), > > + .gdscs = gpu_cc_sm8350_gdscs, > > + .num_gdscs = ARRAY_SIZE(gpu_cc_sm8350_gdscs), > > +}; > > + > > +static int gpu_cc_sm8350_probe(struct platform_device *pdev) > > +{ > > + struct regmap *regmap; > > + > > + regmap = qcom_cc_map(pdev, &gpu_cc_sm8350_desc); > > + if (IS_ERR(regmap)) { > > + dev_err(&pdev->dev, "Failed to map gpu cc registers\n"); > > I think we'd get a probe error even without this, no? Where would that prope error originate? > > > Konrad > > > + return PTR_ERR(regmap); > > + } > > + > > + clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); > > + clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); > > + > > + return qcom_cc_really_probe(pdev, &gpu_cc_sm8350_desc, regmap); > > +} > > + > > +static const struct of_device_id gpu_cc_sm8350_match_table[] = { > > + { .compatible = "qcom,sm8350-gpucc" }, > > + { } > > +}; > > +MODULE_DEVICE_TABLE(of, gpu_cc_sm8350_match_table); > > + > > +static struct platform_driver gpu_cc_sm8350_driver = { > > + .probe = gpu_cc_sm8350_probe, > > + .driver = { > > + .name = "sm8350-gpucc", > > + .of_match_table = gpu_cc_sm8350_match_table, > > + }, > > +}; > > + > > +static int __init gpu_cc_sm8350_init(void) > > +{ > > + return platform_driver_register(&gpu_cc_sm8350_driver); > > +} > > +subsys_initcall(gpu_cc_sm8350_init); > > + > > +static void __exit gpu_cc_sm8350_exit(void) > > +{ > > + platform_driver_unregister(&gpu_cc_sm8350_driver); > > +} > > +module_exit(gpu_cc_sm8350_exit); > > + > > +MODULE_DESCRIPTION("QTI GPU_CC SM8350 Driver"); > > +MODULE_LICENSE("GPL v2"); ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v5 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings 2022-06-09 9:29 [PATCH v5 0/6] SM8350 Display/GPU clock enablement Robert Foss 2022-06-09 9:29 ` [PATCH v5 1/6] arm64: dts: qcom: sm8350: Replace integers with rpmpd defines Robert Foss 2022-06-09 9:29 ` [PATCH v5 2/6] clk: qcom: add support for SM8350 GPUCC Robert Foss @ 2022-06-09 9:29 ` Robert Foss 2022-06-11 18:04 ` kernel test robot 2022-06-14 21:01 ` Rob Herring 2022-06-09 9:29 ` [PATCH v5 4/6] clk: qcom: add support for SM8350 DISPCC Robert Foss ` (2 subsequent siblings) 5 siblings, 2 replies; 13+ messages in thread From: Robert Foss @ 2022-06-09 9:29 UTC (permalink / raw) To: agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt, robert.foss, jonathan, linux-arm-msm, linux-clk, devicetree, linux-kernel, Dmitry Baryshkov, Konrad Dybcio Cc: Dmitry Baryshkov Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8350 SoCs. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmityr.baryshkov@linaro.org> --- Changes since v3 - Separate from qcom,gpucc - Remove clock-names - Make example sm8350 based - Changed author to me due to size of changes .../bindings/clock/qcom,gpucc-sm8350.yaml | 72 +++++++++++++++++++ include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 ++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml new file mode 100644 index 000000000000..0a0546c079a9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller Binding + +maintainers: + - Robert Foss <robert.foss@linaro.org> + +description: | + Qualcomm graphics clock control module which supports the clocks, resets and + power domains on Qualcomm SoCs. + + See also: + dt-bindings/clock/qcom,gpucc-sm8350.h + +properties: + compatible: + enum: + - qcom,sm8350-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm8350.h> + #include <dt-bindings/clock/qcom,rpmh.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d90000 { + compatible = "qcom,sm8350-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8350.h b/include/dt-bindings/clock/qcom,gpucc-sm8350.h new file mode 100644 index 000000000000..2ca857f5bfd2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sm8350.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CX_QDSS_AT_CLK 5 +#define GPU_CC_CX_QDSS_TRIG_CLK 6 +#define GPU_CC_CX_QDSS_TSCTR_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_FREQ_MEASURE_CLK 11 +#define GPU_CC_GMU_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_GX_QDSS_TSCTR_CLK 14 +#define GPU_CC_GX_VSENSE_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21 +#define GPU_CC_MND1X_0_GFX3D_CLK 22 +#define GPU_CC_MND1X_1_GFX3D_CLK 23 +#define GPU_CC_PLL0 24 +#define GPU_CC_PLL1 25 +#define GPU_CC_SLEEP_CLK 26 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif -- 2.34.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v5 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings 2022-06-09 9:29 ` [PATCH v5 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings Robert Foss @ 2022-06-11 18:04 ` kernel test robot 2022-06-14 21:01 ` Rob Herring 1 sibling, 0 replies; 13+ messages in thread From: kernel test robot @ 2022-06-11 18:04 UTC (permalink / raw) To: Robert Foss, agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt, jonathan, linux-arm-msm, linux-clk, devicetree, linux-kernel, Dmitry Baryshkov, Konrad Dybcio Cc: llvm, kbuild-all Hi Robert, I love your patch! Yet something to improve: [auto build test ERROR on clk/clk-next] [also build test ERROR on robh/for-next v5.19-rc1 next-20220610] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/intel-lab-lkp/linux/commits/Robert-Foss/SM8350-Display-GPU-clock-enablement/20220609-173149 base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next config: arm64-buildonly-randconfig-r005-20220611 (https://download.01.org/0day-ci/archive/20220612/202206120103.ptlYOvp4-lkp@intel.com/config) compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project ff4abe755279a3a47cc416ef80dbc900d9a98a19) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm64 cross compiling tool for clang build # apt-get install binutils-aarch64-linux-gnu # https://github.com/intel-lab-lkp/linux/commit/e7acd4b7cc95e3f3ffaa4782f09245b44d4faa31 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Robert-Foss/SM8350-Display-GPU-clock-enablement/20220609-173149 git checkout e7acd4b7cc95e3f3ffaa4782f09245b44d4faa31 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/clk/qcom/ If you fix the issue, kindly add following tag where applicable Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): >> drivers/clk/qcom/gpucc-sm8350.c:111:2: error: initializer element is not a compile-time constant gpu_cc_parent, ^~~~~~~~~~~~~ drivers/clk/qcom/gpucc-sm8350.c:126:2: error: initializer element is not a compile-time constant gpu_cc_parent, ^~~~~~~~~~~~~ 2 errors generated. vim +111 drivers/clk/qcom/gpucc-sm8350.c 05334fe2099d9b Robert Foss 2022-06-09 109 05334fe2099d9b Robert Foss 2022-06-09 110 static const struct clk_parent_data gpu_cc_parent_data_0[] = { 05334fe2099d9b Robert Foss 2022-06-09 @111 gpu_cc_parent, 05334fe2099d9b Robert Foss 2022-06-09 112 { .hw = &gpu_cc_pll0.clkr.hw }, 05334fe2099d9b Robert Foss 2022-06-09 113 { .hw = &gpu_cc_pll1.clkr.hw }, 05334fe2099d9b Robert Foss 2022-06-09 114 { .fw_name = "gcc_gpu_gpll0_clk_src" }, 05334fe2099d9b Robert Foss 2022-06-09 115 { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, 05334fe2099d9b Robert Foss 2022-06-09 116 }; 05334fe2099d9b Robert Foss 2022-06-09 117 -- 0-DAY CI Kernel Test Service https://01.org/lkp ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings 2022-06-09 9:29 ` [PATCH v5 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings Robert Foss 2022-06-11 18:04 ` kernel test robot @ 2022-06-14 21:01 ` Rob Herring 1 sibling, 0 replies; 13+ messages in thread From: Rob Herring @ 2022-06-14 21:01 UTC (permalink / raw) To: Robert Foss Cc: linux-kernel, agross, sboyd, robh+dt, jonathan, Dmitry Baryshkov, devicetree, bjorn.andersson, linux-arm-msm, krzk+dt, Dmitry Baryshkov, mturquette, Konrad Dybcio, linux-clk On Thu, 09 Jun 2022 11:29:37 +0200, Robert Foss wrote: > Add device tree bindings for graphics clock controller for > Qualcomm Technology Inc's SM8350 SoCs. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > Reviewed-by: Dmitry Baryshkov <dmityr.baryshkov@linaro.org> > --- > > Changes since v3 > - Separate from qcom,gpucc > - Remove clock-names > - Make example sm8350 based > - Changed author to me due to size of changes > > > > .../bindings/clock/qcom,gpucc-sm8350.yaml | 72 +++++++++++++++++++ > include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 ++++++++++++++ > 2 files changed, 124 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml > create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v5 4/6] clk: qcom: add support for SM8350 DISPCC 2022-06-09 9:29 [PATCH v5 0/6] SM8350 Display/GPU clock enablement Robert Foss ` (2 preceding siblings ...) 2022-06-09 9:29 ` [PATCH v5 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings Robert Foss @ 2022-06-09 9:29 ` Robert Foss 2022-06-09 10:52 ` Konrad Dybcio 2022-06-09 9:29 ` [PATCH v5 5/6] dt-bindings: clock: Add Qcom SM8350 DISPCC bindings Robert Foss 2022-06-09 9:29 ` [PATCH v5 6/6] arm64: dts: qcom: sm8350: Add DISPCC node Robert Foss 5 siblings, 1 reply; 13+ messages in thread From: Robert Foss @ 2022-06-09 9:29 UTC (permalink / raw) To: agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt, robert.foss, jonathan, linux-arm-msm, linux-clk, devicetree, linux-kernel, Dmitry Baryshkov, Konrad Dybcio Add support to the SM8350 display clock controller. While this controller is similar to the sm8250 controller, the differences are incompatible due to the .fw_name / .index change. Signed-off-by: Robert Foss <robert.foss@linaro.org> --- Changes since v1 - Remove comment - Dmitry Changes since v2 - Add my SoB - Bjorn - Remove CLK_ASSUME_ENABLED_WHEN_UNUSED flag Changes since v3 - Add kconfig dependency on SM_GCC_8350 - Konrad - Change hex to lowercase - Konrad - Split from dispcc-sm8250.c implementation - Switch from .fw_name to .index drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/dispcc-sm8350.c | 1330 ++++++++++++++++++++++++++++++ 3 files changed, 1340 insertions(+) create mode 100644 drivers/clk/qcom/dispcc-sm8350.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index b11235c21952..319812a1d614 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -626,6 +626,15 @@ config SM_DISPCC_8250 Say Y if you want to support display devices and functionality such as splash screen. +config SM_DISPCC_8350 + tristate "SM8350 Display Clock Controller" + depends on SM_GCC_8350 + help + Support for the display clock controller on Qualcomm Technologies, Inc + SM8350 devices. + Say Y if you want to support display devices and functionality such as + splash screen. + config SM_DISPCC_6350 tristate "SM6350 Display Clock Controller" depends on SM_GCC_6350 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index ef9c64824424..70f98320eb1d 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -91,6 +91,7 @@ obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o +obj-$(CONFIG_SM_DISPCC_8350) += dispcc-sm8350.o obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o obj-$(CONFIG_SM_GCC_6350) += gcc-sm6350.o diff --git a/drivers/clk/qcom/dispcc-sm8350.c b/drivers/clk/qcom/dispcc-sm8350.c new file mode 100644 index 000000000000..269a0512f207 --- /dev/null +++ b/drivers/clk/qcom/dispcc-sm8350.c @@ -0,0 +1,1330 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> +#include <linux/reset-controller.h> + +#include <dt-bindings/clock/qcom,dispcc-sm8350.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +/* Need to match the order of clocks in DT binding */ +enum { + DT_BI_TCXO, + DT_DP_PHY_PLL_LINK_CLK, + DT_DP_PHY_PLL_VCO_DIV_CLK, + DT_DPTX1_PHY_PLL_LINK_CLK, + DT_DPTX1_PHY_PLL_VCO_DIV_CLK, + DT_DPTX2_PHY_PLL_LINK_CLK, + DT_DPTX2_PHY_PLL_VCO_DIV_CLK, + DT_DSI0_PHY_PLL_OUT_BYTECLK, + DT_DSI0_PHY_PLL_OUT_DSICLK, + DT_DSI1_PHY_PLL_OUT_BYTECLK, + DT_DSI1_PHY_PLL_OUT_DSICLK, + DT_EDP_PHY_PLL_LINK_CLK, + DT_EDP_PHY_PLL_VCO_DIV_CLK, +}; + +enum { + P_BI_TCXO, + P_DISP_CC_PLL0_OUT_MAIN, + P_DISP_CC_PLL1_OUT_EVEN, + P_DISP_CC_PLL1_OUT_MAIN, + P_DP_PHY_PLL_LINK_CLK, + P_DP_PHY_PLL_VCO_DIV_CLK, + P_DPTX1_PHY_PLL_LINK_CLK, + P_DPTX1_PHY_PLL_VCO_DIV_CLK, + P_DPTX2_PHY_PLL_LINK_CLK, + P_DPTX2_PHY_PLL_VCO_DIV_CLK, + P_EDP_PHY_PLL_LINK_CLK, + P_EDP_PHY_PLL_VCO_DIV_CLK, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_DSI1_PHY_PLL_OUT_BYTECLK, + P_DSI1_PHY_PLL_OUT_DSICLK, +}; + +static struct pll_vco vco_table[] = { + { 249600000, 2000000000, 0 }, +}; + +static struct pll_vco lucid_5lpe_vco[] = { + { 249600000, 1750000000, 0 }, +}; + +static struct alpha_pll_config disp_cc_pll0_config = { + .l = 0x47, + .alpha = 0xE000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x329A699C, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_init_data disp_cc_pll0_init = { + .name = "disp_cc_pll0", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_ops, +}; + +static struct clk_alpha_pll disp_cc_pll0 = { + .offset = 0x0, + .vco_table = vco_table, + .num_vco = ARRAY_SIZE(vco_table), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr.hw.init = &disp_cc_pll0_init +}; + +static struct alpha_pll_config disp_cc_pll1_config = { + .l = 0x1F, + .alpha = 0x4000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x329A699C, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_init_data disp_cc_pll1_init = { + .name = "disp_cc_pll1", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_ops, +}; + +static struct clk_alpha_pll disp_cc_pll1 = { + .offset = 0x1000, + .vco_table = vco_table, + .num_vco = ARRAY_SIZE(vco_table), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr.hw.init = &disp_cc_pll1_init +}; + +static const struct parent_map disp_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_DP_PHY_PLL_LINK_CLK, 1 }, + { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, + { P_DPTX1_PHY_PLL_LINK_CLK, 3 }, + { P_DPTX1_PHY_PLL_VCO_DIV_CLK, 4 }, + { P_DPTX2_PHY_PLL_LINK_CLK, 5 }, + { P_DPTX2_PHY_PLL_VCO_DIV_CLK, 6 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .index = DT_DP_PHY_PLL_LINK_CLK }, + { .index = DT_DP_PHY_PLL_VCO_DIV_CLK }, + { .index = DT_DPTX1_PHY_PLL_LINK_CLK }, + { .index = DT_DPTX1_PHY_PLL_VCO_DIV_CLK }, + { .index = DT_DPTX2_PHY_PLL_LINK_CLK }, + { .index = DT_DPTX2_PHY_PLL_VCO_DIV_CLK }, +}; + +static const struct parent_map disp_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, +}; + +static const struct parent_map disp_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, + { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, + { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map disp_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_3[] = { + { .index = DT_BI_TCXO }, + { .hw = &disp_cc_pll1.clkr.hw }, +}; + +static const struct parent_map disp_cc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_EDP_PHY_PLL_LINK_CLK, 1 }, + { P_EDP_PHY_PLL_VCO_DIV_CLK, 2}, +}; + +static const struct clk_parent_data disp_cc_parent_data_4[] = { + { .index = DT_BI_TCXO }, + { .index = DT_EDP_PHY_PLL_LINK_CLK}, + { .index = DT_EDP_PHY_PLL_VCO_DIV_CLK}, +}; + +static const struct parent_map disp_cc_parent_map_5[] = { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL0_OUT_MAIN, 1 }, + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_5[] = { + { .index = DT_BI_TCXO }, + { .hw = &disp_cc_pll0.clkr.hw }, + { .hw = &disp_cc_pll1.clkr.hw }, +}; + +static const struct parent_map disp_cc_parent_map_6[] = { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_6[] = { + { .index = DT_BI_TCXO }, + { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, + { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, +}; + +static const struct parent_map disp_cc_parent_map_7[] = { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, + /* { P_DISP_CC_PLL1_OUT_EVEN, 5 }, */ +}; + +static const struct clk_parent_data disp_cc_parent_data_7[] = { + { .index = DT_BI_TCXO }, + { .hw = &disp_cc_pll1.clkr.hw }, + /* { .hw = &disp_cc_pll1_out_even.clkr.hw }, */ +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), + F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { + .cmd_rcgr = 0x22bc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_3, + .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_ahb_clk_src", + .parent_data = disp_cc_parent_data_3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { + .cmd_rcgr = 0x210c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_2, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_clk_src", + .parent_data = disp_cc_parent_data_2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { + .cmd_rcgr = 0x2128, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_2, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte1_clk_src", + .parent_data = disp_cc_parent_data_2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = { + .cmd_rcgr = 0x223c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux1_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { + .cmd_rcgr = 0x21d8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = { + .cmd_rcgr = 0x2208, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link1_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), + .ops = &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { + .cmd_rcgr = 0x2174, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), + .ops = &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { + .cmd_rcgr = 0x21c0, + .mnd_width = 16, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel1_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), + .ops = &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = { + .cmd_rcgr = 0x21f0, + .mnd_width = 16, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel2_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), + .ops = &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { + .cmd_rcgr = 0x21a8, + .mnd_width = 16, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), + .ops = &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = { + .cmd_rcgr = 0x228c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_aux_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src = { + .cmd_rcgr = 0x22a4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_7, + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_gtc_clk_src", + .parent_data = disp_cc_parent_data_7, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = { + .cmd_rcgr = 0x2270, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_4, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_link_clk_src", + .parent_data = disp_cc_parent_data_4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = { + .cmd_rcgr = 0x2258, + .mnd_width = 16, + .hid_width = 5, + .parent_map = disp_cc_parent_map_4, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_pixel_clk_src", + .parent_data = disp_cc_parent_data_4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), + .ops = &clk_dp_ops, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_aux_clk = { + .halt_reg = 0x2078, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_aux_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_edp_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_gtc_clk = { + .halt_reg = 0x207c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x207c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_gtc_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_edp_gtc_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_link_clk = { + .halt_reg = 0x2070, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2070, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_link_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_edp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_link_intf_clk = { + .halt_reg = 0x2074, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2074, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_link_intf_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_edp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_pixel_clk = { + .halt_reg = 0x206c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x206c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_pixel_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_edp_pixel_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { + .cmd_rcgr = 0x2144, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_2, + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_esc0_clk_src", + .parent_data = disp_cc_parent_data_2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { + .cmd_rcgr = 0x2160, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_2, + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_esc1_clk_src", + .parent_data = disp_cc_parent_data_2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(85714286, P_DISP_CC_PLL1_OUT_MAIN, 7, 0, 0), + F(100000000, P_DISP_CC_PLL1_OUT_MAIN, 6, 0, 0), + F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0), + F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), + F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { + .cmd_rcgr = 0x20c4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_5, + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_clk_src", + .parent_data = disp_cc_parent_data_5, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { + .cmd_rcgr = 0x2094, + .mnd_width = 8, + .hid_width = 5, + .parent_map = disp_cc_parent_map_6, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_pclk0_clk_src", + .parent_data = disp_cc_parent_data_6, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { + .cmd_rcgr = 0x20ac, + .mnd_width = 8, + .hid_width = 5, + .parent_map = disp_cc_parent_map_6, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_pclk1_clk_src", + .parent_data = disp_cc_parent_data_6, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_pixel_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), + F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { + .cmd_rcgr = 0x20dc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_5, + .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rot_clk_src", + .parent_data = disp_cc_parent_data_5, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { + .cmd_rcgr = 0x20f4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_vsync_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { + .reg = 0x2124, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "disp_cc_mdss_byte0_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { + .reg = 0x2140, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "disp_cc_mdss_byte1_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte1_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = { + .reg = 0x2220, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "disp_cc_mdss_dp_link1_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link1_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = { + .reg = 0x218c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "disp_cc_mdss_dp_link_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch disp_cc_mdss_ahb_clk = { + .halt_reg = 0x207c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x207c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_clk = { + .halt_reg = 0x2028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_intf_clk = { + .halt_reg = 0x202c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x202c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_intf_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte1_clk = { + .halt_reg = 0x2030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte1_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte1_intf_clk = { + .halt_reg = 0x2034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte1_intf_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte1_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_aux1_clk = { + .halt_reg = 0x2068, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2068, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux1_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_aux1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_aux_clk = { + .halt_reg = 0x2054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link1_clk = { + .halt_reg = 0x205c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x205c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link1_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = { + .halt_reg = 0x2060, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link1_intf_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link1_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_clk = { + .halt_reg = 0x2040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { + .halt_reg = 0x2044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_intf_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel1_clk = { + .halt_reg = 0x2050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2050, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel1_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel2_clk = { + .halt_reg = 0x2058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel2_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_pixel2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel_clk = { + .halt_reg = 0x204c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x204c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_esc0_clk = { + .halt_reg = 0x2038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2038, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_esc0_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_esc1_clk = { + .halt_reg = 0x203c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x203c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_esc1_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_esc1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_clk = { + .halt_reg = 0x200c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x200c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_lut_clk = { + .halt_reg = 0x201c, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x201c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_lut_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { + .halt_reg = 0x4004, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x4004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_non_gdsc_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk0_clk = { + .halt_reg = 0x2004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_pclk0_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk1_clk = { + .halt_reg = 0x2008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_pclk1_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_pclk1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rot_clk = { + .halt_reg = 0x2014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rot_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_rot_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { + .halt_reg = 0x400c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x400c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rscc_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { + .halt_reg = 0x4008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rscc_vsync_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_vsync_clk = { + .halt_reg = 0x2024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_vsync_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc mdss_gdsc = { + .gdscr = 0x3000, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "mdss_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = HW_CTRL, + .supply = "mmcx", +}; + +static struct clk_regmap *disp_cc_sm8350_clocks[] = { + [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, + [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, + [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, + [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, + [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, + [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, + [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, + [DISP_CC_MDSS_DP_AUX1_CLK] = &disp_cc_mdss_dp_aux1_clk.clkr, + [DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr, + [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, + [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK1_CLK] = &disp_cc_mdss_dp_link1_clk.clkr, + [DISP_CC_MDSS_DP_LINK1_CLK_SRC] = &disp_cc_mdss_dp_link1_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = &disp_cc_mdss_dp_link1_div_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK1_INTF_CLK] = &disp_cc_mdss_dp_link1_intf_clk.clkr, + [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, + [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dp_link_div_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr, + [DISP_CC_MDSS_DP_PIXEL2_CLK] = &disp_cc_mdss_dp_pixel2_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, + [DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr, + [DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr, + [DISP_CC_MDSS_EDP_GTC_CLK] = &disp_cc_mdss_edp_gtc_clk.clkr, + [DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr, + [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr, + [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr, + [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr, + [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr, + [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr, + [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, + [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, + [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, + [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, + [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, + [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, + [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, + [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, + [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, + [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, + [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, + [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, + [DISP_CC_PLL0] = &disp_cc_pll0.clkr, + [DISP_CC_PLL1] = &disp_cc_pll1.clkr, +}; + +static const struct qcom_reset_map disp_cc_sm8350_resets[] = { + [DISP_CC_MDSS_CORE_BCR] = { 0x2000 }, + [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 }, +}; + +static struct gdsc *disp_cc_sm8350_gdscs[] = { + [MDSS_GDSC] = &mdss_gdsc, +}; + +static const struct regmap_config disp_cc_sm8350_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10000, + .fast_io = true, +}; + +static const struct qcom_cc_desc disp_cc_sm8350_desc = { + .config = &disp_cc_sm8350_regmap_config, + .clks = disp_cc_sm8350_clocks, + .num_clks = ARRAY_SIZE(disp_cc_sm8350_clocks), + .resets = disp_cc_sm8350_resets, + .num_resets = ARRAY_SIZE(disp_cc_sm8350_resets), + .gdscs = disp_cc_sm8350_gdscs, + .num_gdscs = ARRAY_SIZE(disp_cc_sm8350_gdscs), +}; + +static const struct of_device_id disp_cc_sm8350_match_table[] = { + { .compatible = "qcom,sc8180x-dispcc" }, + { .compatible = "qcom,sm8150-dispcc" }, + { .compatible = "qcom,sm8350-dispcc" }, + { .compatible = "qcom,sm8350-dispcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, disp_cc_sm8350_match_table); + +static void disp_cc_sm8350_pm_runtime_disable(void *data) +{ + pm_runtime_disable(data); +} + +static int disp_cc_sm8350_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + pm_runtime_enable(&pdev->dev); + + ret = devm_add_action_or_reset(&pdev->dev, disp_cc_sm8350_pm_runtime_disable, &pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + + regmap = qcom_cc_map(pdev, &disp_cc_sm8350_desc); + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); + return PTR_ERR(regmap); + } + + BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); + + disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0; + + disp_cc_pll0_config.config_ctl_hi1_val = 0x2a9a699c; + disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000; + disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops; + disp_cc_pll0.vco_table = lucid_5lpe_vco; + disp_cc_pll1_config.config_ctl_hi1_val = 0x2a9a699c; + disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000; + disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops; + disp_cc_pll1.vco_table = lucid_5lpe_vco; + + clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); + clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); + + /* Enable clock gating for MDP clocks */ + regmap_update_bits(regmap, 0x8000, 0x10, 0x10); + + /* DISP_CC_XO_CLK always-on */ + regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); + + ret = qcom_cc_really_probe(pdev, &disp_cc_sm8350_desc, regmap); + + pm_runtime_put(&pdev->dev); + + return ret; +} + +static struct platform_driver disp_cc_sm8350_driver = { + .probe = disp_cc_sm8350_probe, + .driver = { + .name = "disp_cc-sm8350", + .of_match_table = disp_cc_sm8350_match_table, + }, +}; + +static int __init disp_cc_sm8350_init(void) +{ + return platform_driver_register(&disp_cc_sm8350_driver); +} +subsys_initcall(disp_cc_sm8350_init); + +static void __exit disp_cc_sm8350_exit(void) +{ + platform_driver_unregister(&disp_cc_sm8350_driver); +} +module_exit(disp_cc_sm8350_exit); + +MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver"); +MODULE_LICENSE("GPL v2"); -- 2.34.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v5 4/6] clk: qcom: add support for SM8350 DISPCC 2022-06-09 9:29 ` [PATCH v5 4/6] clk: qcom: add support for SM8350 DISPCC Robert Foss @ 2022-06-09 10:52 ` Konrad Dybcio 2022-06-09 12:58 ` Robert Foss 0 siblings, 1 reply; 13+ messages in thread From: Konrad Dybcio @ 2022-06-09 10:52 UTC (permalink / raw) To: Robert Foss, agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt, jonathan, linux-arm-msm, linux-clk, devicetree, linux-kernel, Dmitry Baryshkov Hi! On 09/06/2022 11:29, Robert Foss wrote: > Add support to the SM8350 display clock controller. > > While this controller is similar to the sm8250 controller, the differences > are incompatible due to the .fw_name / .index change. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- > > > Changes since v1 > - Remove comment - Dmitry > > Changes since v2 > - Add my SoB - Bjorn > - Remove CLK_ASSUME_ENABLED_WHEN_UNUSED flag > > Changes since v3 > - Add kconfig dependency on SM_GCC_8350 - Konrad > - Change hex to lowercase - Konrad > - Split from dispcc-sm8250.c implementation > - Switch from .fw_name to .index > > > drivers/clk/qcom/Kconfig | 9 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/dispcc-sm8350.c | 1330 ++++++++++++++++++++++++++++++ > 3 files changed, 1340 insertions(+) > create mode 100644 drivers/clk/qcom/dispcc-sm8350.c > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index b11235c21952..319812a1d614 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -626,6 +626,15 @@ config SM_DISPCC_8250 > Say Y if you want to support display devices and functionality such as > splash screen. > > +config SM_DISPCC_8350 > + tristate "SM8350 Display Clock Controller" > + depends on SM_GCC_8350 > + help > + Support for the display clock controller on Qualcomm Technologies, Inc > + SM8350 devices. > + Say Y if you want to support display devices and functionality such as > + splash screen. > + > config SM_DISPCC_6350 > tristate "SM6350 Display Clock Controller" > depends on SM_GCC_6350 > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index ef9c64824424..70f98320eb1d 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -91,6 +91,7 @@ obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o > obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o > obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o > obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o > +obj-$(CONFIG_SM_DISPCC_8350) += dispcc-sm8350.o > obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o > obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o > obj-$(CONFIG_SM_GCC_6350) += gcc-sm6350.o > diff --git a/drivers/clk/qcom/dispcc-sm8350.c b/drivers/clk/qcom/dispcc-sm8350.c > new file mode 100644 > index 000000000000..269a0512f207 > --- /dev/null > +++ b/drivers/clk/qcom/dispcc-sm8350.c > @@ -0,0 +1,1330 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2022, The Linux Foundation. All rights reserved. > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/pm_runtime.h> > +#include <linux/regmap.h> > +#include <linux/reset-controller.h> > + > +#include <dt-bindings/clock/qcom,dispcc-sm8350.h> > + > +#include "clk-alpha-pll.h" > +#include "clk-branch.h" > +#include "clk-rcg.h" > +#include "clk-regmap-divider.h" > +#include "common.h" > +#include "gdsc.h" > +#include "reset.h" > + > +/* Need to match the order of clocks in DT binding */ > +enum { > + DT_BI_TCXO, > + DT_DP_PHY_PLL_LINK_CLK, > + DT_DP_PHY_PLL_VCO_DIV_CLK, > + DT_DPTX1_PHY_PLL_LINK_CLK, > + DT_DPTX1_PHY_PLL_VCO_DIV_CLK, > + DT_DPTX2_PHY_PLL_LINK_CLK, > + DT_DPTX2_PHY_PLL_VCO_DIV_CLK, > + DT_DSI0_PHY_PLL_OUT_BYTECLK, > + DT_DSI0_PHY_PLL_OUT_DSICLK, > + DT_DSI1_PHY_PLL_OUT_BYTECLK, > + DT_DSI1_PHY_PLL_OUT_DSICLK, > + DT_EDP_PHY_PLL_LINK_CLK, > + DT_EDP_PHY_PLL_VCO_DIV_CLK, > +}; > + > +enum { > + P_BI_TCXO, > + P_DISP_CC_PLL0_OUT_MAIN, > + P_DISP_CC_PLL1_OUT_EVEN, > + P_DISP_CC_PLL1_OUT_MAIN, > + P_DP_PHY_PLL_LINK_CLK, > + P_DP_PHY_PLL_VCO_DIV_CLK, > + P_DPTX1_PHY_PLL_LINK_CLK, > + P_DPTX1_PHY_PLL_VCO_DIV_CLK, > + P_DPTX2_PHY_PLL_LINK_CLK, > + P_DPTX2_PHY_PLL_VCO_DIV_CLK, > + P_EDP_PHY_PLL_LINK_CLK, > + P_EDP_PHY_PLL_VCO_DIV_CLK, > + P_DSI0_PHY_PLL_OUT_BYTECLK, > + P_DSI0_PHY_PLL_OUT_DSICLK, > + P_DSI1_PHY_PLL_OUT_BYTECLK, > + P_DSI1_PHY_PLL_OUT_DSICLK, > +}; > + > +static struct pll_vco vco_table[] = { > + { 249600000, 2000000000, 0 }, > +}; > + > +static struct pll_vco lucid_5lpe_vco[] = { > + { 249600000, 1750000000, 0 }, > +}; > + > +static struct alpha_pll_config disp_cc_pll0_config = { > + .l = 0x47, > + .alpha = 0xE000, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00002261, > + .config_ctl_hi1_val = 0x329A699C, Lowercase hex please, all around the file > + .user_ctl_val = 0x00000000, > + .user_ctl_hi_val = 0x00000805, > + .user_ctl_hi1_val = 0x00000000, > +}; > + > +static struct clk_init_data disp_cc_pll0_init = { > + .name = "disp_cc_pll0", > + .parent_data = &(const struct clk_parent_data){ > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_ops, > +}; > + > +static struct clk_alpha_pll disp_cc_pll0 = { > + .offset = 0x0, > + .vco_table = vco_table, > + .num_vco = ARRAY_SIZE(vco_table), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > + .clkr.hw.init = &disp_cc_pll0_init > +}; > + > +static struct alpha_pll_config disp_cc_pll1_config = { > + .l = 0x1F, > + .alpha = 0x4000, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00002261, > + .config_ctl_hi1_val = 0x329A699C, > + .user_ctl_val = 0x00000000, > + .user_ctl_hi_val = 0x00000805, > + .user_ctl_hi1_val = 0x00000000, > +}; > + > +static struct clk_init_data disp_cc_pll1_init = { > + .name = "disp_cc_pll1", > + .parent_data = &(const struct clk_parent_data){ > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_ops, > +}; > + > +static struct clk_alpha_pll disp_cc_pll1 = { > + .offset = 0x1000, > + .vco_table = vco_table, > + .num_vco = ARRAY_SIZE(vco_table), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > + .clkr.hw.init = &disp_cc_pll1_init > +}; > + > +static const struct parent_map disp_cc_parent_map_0[] = { > + { P_BI_TCXO, 0 }, > + { P_DP_PHY_PLL_LINK_CLK, 1 }, > + { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, > + { P_DPTX1_PHY_PLL_LINK_CLK, 3 }, > + { P_DPTX1_PHY_PLL_VCO_DIV_CLK, 4 }, > + { P_DPTX2_PHY_PLL_LINK_CLK, 5 }, > + { P_DPTX2_PHY_PLL_VCO_DIV_CLK, 6 }, > +}; > + > +static const struct clk_parent_data disp_cc_parent_data_0[] = { > + { .index = DT_BI_TCXO }, > + { .index = DT_DP_PHY_PLL_LINK_CLK }, > + { .index = DT_DP_PHY_PLL_VCO_DIV_CLK }, > + { .index = DT_DPTX1_PHY_PLL_LINK_CLK }, > + { .index = DT_DPTX1_PHY_PLL_VCO_DIV_CLK }, > + { .index = DT_DPTX2_PHY_PLL_LINK_CLK }, > + { .index = DT_DPTX2_PHY_PLL_VCO_DIV_CLK }, > +}; > + > +static const struct parent_map disp_cc_parent_map_1[] = { > + { P_BI_TCXO, 0 }, > +}; > + > +static const struct clk_parent_data disp_cc_parent_data_1[] = { > + { .index = DT_BI_TCXO }, > +}; > + > +static const struct parent_map disp_cc_parent_map_2[] = { > + { P_BI_TCXO, 0 }, > + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, > + { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 }, > +}; > + > +static const struct clk_parent_data disp_cc_parent_data_2[] = { > + { .index = DT_BI_TCXO }, > + { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, > + { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, > +}; > + > +static const struct parent_map disp_cc_parent_map_3[] = { > + { P_BI_TCXO, 0 }, > + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, > +}; > + > +static const struct clk_parent_data disp_cc_parent_data_3[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &disp_cc_pll1.clkr.hw }, > +}; > + > +static const struct parent_map disp_cc_parent_map_4[] = { > + { P_BI_TCXO, 0 }, > + { P_EDP_PHY_PLL_LINK_CLK, 1 }, > + { P_EDP_PHY_PLL_VCO_DIV_CLK, 2}, > +}; > + > +static const struct clk_parent_data disp_cc_parent_data_4[] = { > + { .index = DT_BI_TCXO }, > + { .index = DT_EDP_PHY_PLL_LINK_CLK}, > + { .index = DT_EDP_PHY_PLL_VCO_DIV_CLK}, > +}; > + > +static const struct parent_map disp_cc_parent_map_5[] = { > + { P_BI_TCXO, 0 }, > + { P_DISP_CC_PLL0_OUT_MAIN, 1 }, > + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, > +}; > + > +static const struct clk_parent_data disp_cc_parent_data_5[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &disp_cc_pll0.clkr.hw }, > + { .hw = &disp_cc_pll1.clkr.hw }, > +}; > + > +static const struct parent_map disp_cc_parent_map_6[] = { > + { P_BI_TCXO, 0 }, > + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, > + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, > +}; > + > +static const struct clk_parent_data disp_cc_parent_data_6[] = { > + { .index = DT_BI_TCXO }, > + { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, > + { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, > +}; > + > +static const struct parent_map disp_cc_parent_map_7[] = { > + { P_BI_TCXO, 0 }, > + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, > + /* { P_DISP_CC_PLL1_OUT_EVEN, 5 }, */ Is this and its .hw below commented out on purpose? If so, why? > +}; > + > +static const struct clk_parent_data disp_cc_parent_data_7[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &disp_cc_pll1.clkr.hw }, > + /* { .hw = &disp_cc_pll1_out_even.clkr.hw }, */ > +}; > + > +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), > + F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { > + .cmd_rcgr = 0x22bc, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_3, > + .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_ahb_clk_src", > + .parent_data = disp_cc_parent_data_3, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { > + .cmd_rcgr = 0x210c, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_2, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_byte0_clk_src", > + .parent_data = disp_cc_parent_data_2, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_byte2_ops, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { > + .cmd_rcgr = 0x2128, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_2, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_byte1_clk_src", > + .parent_data = disp_cc_parent_data_2, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_byte2_ops, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = { > + .cmd_rcgr = 0x223c, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_1, > + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_aux1_clk_src", > + .parent_data = disp_cc_parent_data_1, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { > + .cmd_rcgr = 0x21d8, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_1, > + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_aux_clk_src", > + .parent_data = disp_cc_parent_data_1, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = { > + .cmd_rcgr = 0x2208, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_0, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_link1_clk_src", > + .parent_data = disp_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > + .ops = &clk_byte2_ops, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { > + .cmd_rcgr = 0x2174, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_0, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_link_clk_src", > + .parent_data = disp_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > + .ops = &clk_byte2_ops, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { > + .cmd_rcgr = 0x21c0, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_0, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_pixel1_clk_src", > + .parent_data = disp_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > + .ops = &clk_dp_ops, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = { > + .cmd_rcgr = 0x21f0, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_0, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_pixel2_clk_src", > + .parent_data = disp_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > + .ops = &clk_dp_ops, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { > + .cmd_rcgr = 0x21a8, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_0, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_pixel_clk_src", > + .parent_data = disp_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > + .ops = &clk_dp_ops, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = { > + .cmd_rcgr = 0x228c, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_1, > + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_edp_aux_clk_src", > + .parent_data = disp_cc_parent_data_1, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src = { > + .cmd_rcgr = 0x22a4, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_7, > + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_edp_gtc_clk_src", > + .parent_data = disp_cc_parent_data_7, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = { > + .cmd_rcgr = 0x2270, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_4, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_edp_link_clk_src", > + .parent_data = disp_cc_parent_data_4, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_byte2_ops, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = { > + .cmd_rcgr = 0x2258, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_4, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_edp_pixel_clk_src", > + .parent_data = disp_cc_parent_data_4, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), > + .ops = &clk_dp_ops, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_edp_aux_clk = { > + .halt_reg = 0x2078, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2078, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_edp_aux_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_edp_aux_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_edp_gtc_clk = { > + .halt_reg = 0x207c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x207c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_edp_gtc_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_edp_gtc_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_edp_link_clk = { > + .halt_reg = 0x2070, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2070, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_edp_link_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_edp_link_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_edp_link_intf_clk = { > + .halt_reg = 0x2074, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2074, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_edp_link_intf_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_edp_link_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_GET_RATE_NOCACHE, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_edp_pixel_clk = { > + .halt_reg = 0x206c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x206c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_edp_pixel_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_edp_pixel_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { > + .cmd_rcgr = 0x2144, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_2, > + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_esc0_clk_src", > + .parent_data = disp_cc_parent_data_2, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { > + .cmd_rcgr = 0x2160, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_2, > + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_esc1_clk_src", > + .parent_data = disp_cc_parent_data_2, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(85714286, P_DISP_CC_PLL1_OUT_MAIN, 7, 0, 0), > + F(100000000, P_DISP_CC_PLL1_OUT_MAIN, 6, 0, 0), > + F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0), > + F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), > + F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), > + F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), > + F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { > + .cmd_rcgr = 0x20c4, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_5, > + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_mdp_clk_src", > + .parent_data = disp_cc_parent_data_5, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { > + .cmd_rcgr = 0x2094, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_6, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_pclk0_clk_src", > + .parent_data = disp_cc_parent_data_6, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_pixel_ops, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { > + .cmd_rcgr = 0x20ac, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_6, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_pclk1_clk_src", > + .parent_data = disp_cc_parent_data_6, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_pixel_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), > + F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), > + F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), > + F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { > + .cmd_rcgr = 0x20dc, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_5, > + .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_rot_clk_src", > + .parent_data = disp_cc_parent_data_5, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { > + .cmd_rcgr = 0x20f4, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_1, > + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_vsync_clk_src", > + .parent_data = disp_cc_parent_data_1, > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { > + .reg = 0x2124, > + .shift = 0, > + .width = 4, > + .clkr.hw.init = &(struct clk_init_data) { > + .name = "disp_cc_mdss_byte0_div_clk_src", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_byte0_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .ops = &clk_regmap_div_ops, > + }, > +}; > + > +static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { > + .reg = 0x2140, > + .shift = 0, > + .width = 4, > + .clkr.hw.init = &(struct clk_init_data) { > + .name = "disp_cc_mdss_byte1_div_clk_src", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_byte1_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .ops = &clk_regmap_div_ops, > + }, > +}; > + > +static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = { > + .reg = 0x2220, > + .shift = 0, > + .width = 4, > + .clkr.hw.init = &(struct clk_init_data) { > + .name = "disp_cc_mdss_dp_link1_div_clk_src", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_dp_link1_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .ops = &clk_regmap_div_ro_ops, > + }, > +}; > + > +static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = { > + .reg = 0x218c, > + .shift = 0, > + .width = 4, > + .clkr.hw.init = &(struct clk_init_data) { > + .name = "disp_cc_mdss_dp_link_div_clk_src", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_dp_link_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .ops = &clk_regmap_div_ro_ops, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_ahb_clk = { > + .halt_reg = 0x207c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x207c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_ahb_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_byte0_clk = { > + .halt_reg = 0x2028, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2028, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_byte0_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_byte0_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_byte0_intf_clk = { > + .halt_reg = 0x202c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x202c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_byte0_intf_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_byte1_clk = { > + .halt_reg = 0x2030, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2030, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_byte1_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_byte1_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_byte1_intf_clk = { > + .halt_reg = 0x2034, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2034, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_byte1_intf_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_byte1_div_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_dp_aux1_clk = { > + .halt_reg = 0x2068, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2068, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_aux1_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_dp_aux1_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_dp_aux_clk = { > + .halt_reg = 0x2054, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2054, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_aux_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_dp_aux_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_dp_link1_clk = { > + .halt_reg = 0x205c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x205c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_link1_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_dp_link1_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = { > + .halt_reg = 0x2060, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2060, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_link1_intf_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_dp_link1_div_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_dp_link_clk = { > + .halt_reg = 0x2040, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2040, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_link_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_dp_link_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { > + .halt_reg = 0x2044, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2044, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_link_intf_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_dp_pixel1_clk = { > + .halt_reg = 0x2050, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2050, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_pixel1_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_dp_pixel2_clk = { > + .halt_reg = 0x2058, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2058, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_pixel2_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_dp_pixel2_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_dp_pixel_clk = { > + .halt_reg = 0x204c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x204c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_pixel_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_esc0_clk = { > + .halt_reg = 0x2038, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2038, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_esc0_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_esc0_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_esc1_clk = { > + .halt_reg = 0x203c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x203c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_esc1_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_esc1_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_mdp_clk = { > + .halt_reg = 0x200c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x200c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_mdp_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_mdp_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_mdp_lut_clk = { > + .halt_reg = 0x201c, > + .halt_check = BRANCH_VOTED, > + .clkr = { > + .enable_reg = 0x201c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_mdp_lut_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_mdp_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { > + .halt_reg = 0x4004, > + .halt_check = BRANCH_VOTED, > + .clkr = { > + .enable_reg = 0x4004, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_non_gdsc_ahb_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_pclk0_clk = { > + .halt_reg = 0x2004, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2004, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_pclk0_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_pclk0_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_pclk1_clk = { > + .halt_reg = 0x2008, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2008, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_pclk1_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_pclk1_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_rot_clk = { > + .halt_reg = 0x2014, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2014, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_rot_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_rot_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { > + .halt_reg = 0x400c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x400c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_rscc_ahb_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_ahb_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { > + .halt_reg = 0x4008, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x4008, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_rscc_vsync_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_vsync_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_vsync_clk = { > + .halt_reg = 0x2024, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2024, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_vsync_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &disp_cc_mdss_vsync_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct gdsc mdss_gdsc = { > + .gdscr = 0x3000, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > + .pd = { > + .name = "mdss_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = HW_CTRL, > + .supply = "mmcx", > +}; > + > +static struct clk_regmap *disp_cc_sm8350_clocks[] = { > + [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, > + [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, > + [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, > + [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, > + [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, > + [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, > + [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, > + [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, > + [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, > + [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, > + [DISP_CC_MDSS_DP_AUX1_CLK] = &disp_cc_mdss_dp_aux1_clk.clkr, > + [DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr, > + [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, > + [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, > + [DISP_CC_MDSS_DP_LINK1_CLK] = &disp_cc_mdss_dp_link1_clk.clkr, > + [DISP_CC_MDSS_DP_LINK1_CLK_SRC] = &disp_cc_mdss_dp_link1_clk_src.clkr, > + [DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = &disp_cc_mdss_dp_link1_div_clk_src.clkr, > + [DISP_CC_MDSS_DP_LINK1_INTF_CLK] = &disp_cc_mdss_dp_link1_intf_clk.clkr, > + [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, > + [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, > + [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dp_link_div_clk_src.clkr, > + [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, > + [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr, > + [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr, > + [DISP_CC_MDSS_DP_PIXEL2_CLK] = &disp_cc_mdss_dp_pixel2_clk.clkr, > + [DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr, > + [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, > + [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, > + [DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr, > + [DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr, > + [DISP_CC_MDSS_EDP_GTC_CLK] = &disp_cc_mdss_edp_gtc_clk.clkr, > + [DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr, > + [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr, > + [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr, > + [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr, > + [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr, > + [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr, > + [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, > + [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, > + [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, > + [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, > + [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, > + [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, > + [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, > + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, > + [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, > + [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, > + [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, > + [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, > + [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, > + [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, > + [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, > + [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, > + [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, > + [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, > + [DISP_CC_PLL0] = &disp_cc_pll0.clkr, > + [DISP_CC_PLL1] = &disp_cc_pll1.clkr, > +}; > + > +static const struct qcom_reset_map disp_cc_sm8350_resets[] = { > + [DISP_CC_MDSS_CORE_BCR] = { 0x2000 }, > + [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 }, > +}; > + > +static struct gdsc *disp_cc_sm8350_gdscs[] = { > + [MDSS_GDSC] = &mdss_gdsc, > +}; > + > +static const struct regmap_config disp_cc_sm8350_regmap_config = { > + .reg_bits = 32, > + .reg_stride = 4, > + .val_bits = 32, > + .max_register = 0x10000, > + .fast_io = true, > +}; > + > +static const struct qcom_cc_desc disp_cc_sm8350_desc = { > + .config = &disp_cc_sm8350_regmap_config, > + .clks = disp_cc_sm8350_clocks, > + .num_clks = ARRAY_SIZE(disp_cc_sm8350_clocks), > + .resets = disp_cc_sm8350_resets, > + .num_resets = ARRAY_SIZE(disp_cc_sm8350_resets), > + .gdscs = disp_cc_sm8350_gdscs, > + .num_gdscs = ARRAY_SIZE(disp_cc_sm8350_gdscs), > +}; > + > +static const struct of_device_id disp_cc_sm8350_match_table[] = { > + { .compatible = "qcom,sc8180x-dispcc" }, > + { .compatible = "qcom,sm8150-dispcc" }, > + { .compatible = "qcom,sm8350-dispcc" }, > + { .compatible = "qcom,sm8350-dispcc" }, Double 8350 and mis-copied 8180x/8150 Konrad > + { } > +}; > +MODULE_DEVICE_TABLE(of, disp_cc_sm8350_match_table); > + > +static void disp_cc_sm8350_pm_runtime_disable(void *data) > +{ > + pm_runtime_disable(data); > +} > + > +static int disp_cc_sm8350_probe(struct platform_device *pdev) > +{ > + struct regmap *regmap; > + int ret; > + > + pm_runtime_enable(&pdev->dev); > + > + ret = devm_add_action_or_reset(&pdev->dev, disp_cc_sm8350_pm_runtime_disable, &pdev->dev); > + if (ret) > + return ret; > + > + ret = pm_runtime_resume_and_get(&pdev->dev); > + if (ret) > + return ret; > + > + regmap = qcom_cc_map(pdev, &disp_cc_sm8350_desc); > + if (IS_ERR(regmap)) { > + pm_runtime_put(&pdev->dev); > + return PTR_ERR(regmap); > + } > + > + BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); > + > + disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0; > + > + disp_cc_pll0_config.config_ctl_hi1_val = 0x2a9a699c; > + disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000; > + disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops; > + disp_cc_pll0.vco_table = lucid_5lpe_vco; > + disp_cc_pll1_config.config_ctl_hi1_val = 0x2a9a699c; > + disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000; > + disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops; > + disp_cc_pll1.vco_table = lucid_5lpe_vco; > + > + clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); > + clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); > + > + /* Enable clock gating for MDP clocks */ > + regmap_update_bits(regmap, 0x8000, 0x10, 0x10); > + > + /* DISP_CC_XO_CLK always-on */ > + regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); > + > + ret = qcom_cc_really_probe(pdev, &disp_cc_sm8350_desc, regmap); > + > + pm_runtime_put(&pdev->dev); > + > + return ret; > +} > + > +static struct platform_driver disp_cc_sm8350_driver = { > + .probe = disp_cc_sm8350_probe, > + .driver = { > + .name = "disp_cc-sm8350", > + .of_match_table = disp_cc_sm8350_match_table, > + }, > +}; > + > +static int __init disp_cc_sm8350_init(void) > +{ > + return platform_driver_register(&disp_cc_sm8350_driver); > +} > +subsys_initcall(disp_cc_sm8350_init); > + > +static void __exit disp_cc_sm8350_exit(void) > +{ > + platform_driver_unregister(&disp_cc_sm8350_driver); > +} > +module_exit(disp_cc_sm8350_exit); > + > +MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver"); > +MODULE_LICENSE("GPL v2"); ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5 4/6] clk: qcom: add support for SM8350 DISPCC 2022-06-09 10:52 ` Konrad Dybcio @ 2022-06-09 12:58 ` Robert Foss 0 siblings, 0 replies; 13+ messages in thread From: Robert Foss @ 2022-06-09 12:58 UTC (permalink / raw) To: Konrad Dybcio, Bjorn Andersson Cc: agross, mturquette, sboyd, robh+dt, krzk+dt, jonathan, linux-arm-msm, linux-clk, devicetree, linux-kernel, Dmitry Baryshkov On Thu, 9 Jun 2022 at 12:52, Konrad Dybcio <konrad.dybcio@somainline.org> wrote: > > Hi! > > On 09/06/2022 11:29, Robert Foss wrote: > > Add support to the SM8350 display clock controller. > > > > While this controller is similar to the sm8250 controller, the differences > > are incompatible due to the .fw_name / .index change. > > > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > > --- > > > > > > Changes since v1 > > - Remove comment - Dmitry > > > > Changes since v2 > > - Add my SoB - Bjorn > > - Remove CLK_ASSUME_ENABLED_WHEN_UNUSED flag > > > > Changes since v3 > > - Add kconfig dependency on SM_GCC_8350 - Konrad > > - Change hex to lowercase - Konrad > > - Split from dispcc-sm8250.c implementation > > - Switch from .fw_name to .index > > > > > > drivers/clk/qcom/Kconfig | 9 + > > drivers/clk/qcom/Makefile | 1 + > > drivers/clk/qcom/dispcc-sm8350.c | 1330 ++++++++++++++++++++++++++++++ > > 3 files changed, 1340 insertions(+) > > create mode 100644 drivers/clk/qcom/dispcc-sm8350.c > > > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > > index b11235c21952..319812a1d614 100644 > > --- a/drivers/clk/qcom/Kconfig > > +++ b/drivers/clk/qcom/Kconfig > > @@ -626,6 +626,15 @@ config SM_DISPCC_8250 > > Say Y if you want to support display devices and functionality such as > > splash screen. > > > > +config SM_DISPCC_8350 > > + tristate "SM8350 Display Clock Controller" > > + depends on SM_GCC_8350 > > + help > > + Support for the display clock controller on Qualcomm Technologies, Inc > > + SM8350 devices. > > + Say Y if you want to support display devices and functionality such as > > + splash screen. > > + > > config SM_DISPCC_6350 > > tristate "SM6350 Display Clock Controller" > > depends on SM_GCC_6350 > > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > > index ef9c64824424..70f98320eb1d 100644 > > --- a/drivers/clk/qcom/Makefile > > +++ b/drivers/clk/qcom/Makefile > > @@ -91,6 +91,7 @@ obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o > > obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o > > obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o > > obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o > > +obj-$(CONFIG_SM_DISPCC_8350) += dispcc-sm8350.o > > obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o > > obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o > > obj-$(CONFIG_SM_GCC_6350) += gcc-sm6350.o > > diff --git a/drivers/clk/qcom/dispcc-sm8350.c b/drivers/clk/qcom/dispcc-sm8350.c > > new file mode 100644 > > index 000000000000..269a0512f207 > > --- /dev/null > > +++ b/drivers/clk/qcom/dispcc-sm8350.c > > @@ -0,0 +1,1330 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (c) 2022, The Linux Foundation. All rights reserved. > > + */ > > + > > +#include <linux/clk-provider.h> > > +#include <linux/module.h> > > +#include <linux/platform_device.h> > > +#include <linux/pm_runtime.h> > > +#include <linux/regmap.h> > > +#include <linux/reset-controller.h> > > + > > +#include <dt-bindings/clock/qcom,dispcc-sm8350.h> > > + > > +#include "clk-alpha-pll.h" > > +#include "clk-branch.h" > > +#include "clk-rcg.h" > > +#include "clk-regmap-divider.h" > > +#include "common.h" > > +#include "gdsc.h" > > +#include "reset.h" > > + > > +/* Need to match the order of clocks in DT binding */ > > +enum { > > + DT_BI_TCXO, > > + DT_DP_PHY_PLL_LINK_CLK, > > + DT_DP_PHY_PLL_VCO_DIV_CLK, > > + DT_DPTX1_PHY_PLL_LINK_CLK, > > + DT_DPTX1_PHY_PLL_VCO_DIV_CLK, > > + DT_DPTX2_PHY_PLL_LINK_CLK, > > + DT_DPTX2_PHY_PLL_VCO_DIV_CLK, > > + DT_DSI0_PHY_PLL_OUT_BYTECLK, > > + DT_DSI0_PHY_PLL_OUT_DSICLK, > > + DT_DSI1_PHY_PLL_OUT_BYTECLK, > > + DT_DSI1_PHY_PLL_OUT_DSICLK, > > + DT_EDP_PHY_PLL_LINK_CLK, > > + DT_EDP_PHY_PLL_VCO_DIV_CLK, > > +}; > > + > > +enum { > > + P_BI_TCXO, > > + P_DISP_CC_PLL0_OUT_MAIN, > > + P_DISP_CC_PLL1_OUT_EVEN, > > + P_DISP_CC_PLL1_OUT_MAIN, > > + P_DP_PHY_PLL_LINK_CLK, > > + P_DP_PHY_PLL_VCO_DIV_CLK, > > + P_DPTX1_PHY_PLL_LINK_CLK, > > + P_DPTX1_PHY_PLL_VCO_DIV_CLK, > > + P_DPTX2_PHY_PLL_LINK_CLK, > > + P_DPTX2_PHY_PLL_VCO_DIV_CLK, > > + P_EDP_PHY_PLL_LINK_CLK, > > + P_EDP_PHY_PLL_VCO_DIV_CLK, > > + P_DSI0_PHY_PLL_OUT_BYTECLK, > > + P_DSI0_PHY_PLL_OUT_DSICLK, > > + P_DSI1_PHY_PLL_OUT_BYTECLK, > > + P_DSI1_PHY_PLL_OUT_DSICLK, > > +}; > > + > > +static struct pll_vco vco_table[] = { > > + { 249600000, 2000000000, 0 }, > > +}; > > + > > +static struct pll_vco lucid_5lpe_vco[] = { > > + { 249600000, 1750000000, 0 }, > > +}; > > + > > +static struct alpha_pll_config disp_cc_pll0_config = { > > + .l = 0x47, > > + .alpha = 0xE000, > > + .config_ctl_val = 0x20485699, > > + .config_ctl_hi_val = 0x00002261, > > + .config_ctl_hi1_val = 0x329A699C, > > Lowercase hex please, all around the file Ack. > > > > + .user_ctl_val = 0x00000000, > > + .user_ctl_hi_val = 0x00000805, > > + .user_ctl_hi1_val = 0x00000000, > > +}; > > + > > +static struct clk_init_data disp_cc_pll0_init = { > > + .name = "disp_cc_pll0", > > + .parent_data = &(const struct clk_parent_data){ > > + .index = DT_BI_TCXO, > > + }, > > + .num_parents = 1, > > + .ops = &clk_alpha_pll_lucid_ops, > > +}; > > + > > +static struct clk_alpha_pll disp_cc_pll0 = { > > + .offset = 0x0, > > + .vco_table = vco_table, > > + .num_vco = ARRAY_SIZE(vco_table), > > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > > + .clkr.hw.init = &disp_cc_pll0_init > > +}; > > + > > +static struct alpha_pll_config disp_cc_pll1_config = { > > + .l = 0x1F, > > + .alpha = 0x4000, > > + .config_ctl_val = 0x20485699, > > + .config_ctl_hi_val = 0x00002261, > > + .config_ctl_hi1_val = 0x329A699C, > > + .user_ctl_val = 0x00000000, > > + .user_ctl_hi_val = 0x00000805, > > + .user_ctl_hi1_val = 0x00000000, > > +}; > > + > > +static struct clk_init_data disp_cc_pll1_init = { > > + .name = "disp_cc_pll1", > > + .parent_data = &(const struct clk_parent_data){ > > + .index = DT_BI_TCXO, > > + }, > > + .num_parents = 1, > > + .ops = &clk_alpha_pll_lucid_ops, > > +}; > > + > > +static struct clk_alpha_pll disp_cc_pll1 = { > > + .offset = 0x1000, > > + .vco_table = vco_table, > > + .num_vco = ARRAY_SIZE(vco_table), > > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > > + .clkr.hw.init = &disp_cc_pll1_init > > +}; > > + > > +static const struct parent_map disp_cc_parent_map_0[] = { > > + { P_BI_TCXO, 0 }, > > + { P_DP_PHY_PLL_LINK_CLK, 1 }, > > + { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, > > + { P_DPTX1_PHY_PLL_LINK_CLK, 3 }, > > + { P_DPTX1_PHY_PLL_VCO_DIV_CLK, 4 }, > > + { P_DPTX2_PHY_PLL_LINK_CLK, 5 }, > > + { P_DPTX2_PHY_PLL_VCO_DIV_CLK, 6 }, > > +}; > > + > > +static const struct clk_parent_data disp_cc_parent_data_0[] = { > > + { .index = DT_BI_TCXO }, > > + { .index = DT_DP_PHY_PLL_LINK_CLK }, > > + { .index = DT_DP_PHY_PLL_VCO_DIV_CLK }, > > + { .index = DT_DPTX1_PHY_PLL_LINK_CLK }, > > + { .index = DT_DPTX1_PHY_PLL_VCO_DIV_CLK }, > > + { .index = DT_DPTX2_PHY_PLL_LINK_CLK }, > > + { .index = DT_DPTX2_PHY_PLL_VCO_DIV_CLK }, > > +}; > > + > > +static const struct parent_map disp_cc_parent_map_1[] = { > > + { P_BI_TCXO, 0 }, > > +}; > > + > > +static const struct clk_parent_data disp_cc_parent_data_1[] = { > > + { .index = DT_BI_TCXO }, > > +}; > > + > > +static const struct parent_map disp_cc_parent_map_2[] = { > > + { P_BI_TCXO, 0 }, > > + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, > > + { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 }, > > +}; > > + > > +static const struct clk_parent_data disp_cc_parent_data_2[] = { > > + { .index = DT_BI_TCXO }, > > + { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, > > + { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, > > +}; > > + > > +static const struct parent_map disp_cc_parent_map_3[] = { > > + { P_BI_TCXO, 0 }, > > + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, > > +}; > > + > > +static const struct clk_parent_data disp_cc_parent_data_3[] = { > > + { .index = DT_BI_TCXO }, > > + { .hw = &disp_cc_pll1.clkr.hw }, > > +}; > > + > > +static const struct parent_map disp_cc_parent_map_4[] = { > > + { P_BI_TCXO, 0 }, > > + { P_EDP_PHY_PLL_LINK_CLK, 1 }, > > + { P_EDP_PHY_PLL_VCO_DIV_CLK, 2}, > > +}; > > + > > +static const struct clk_parent_data disp_cc_parent_data_4[] = { > > + { .index = DT_BI_TCXO }, > > + { .index = DT_EDP_PHY_PLL_LINK_CLK}, > > + { .index = DT_EDP_PHY_PLL_VCO_DIV_CLK}, > > +}; > > + > > +static const struct parent_map disp_cc_parent_map_5[] = { > > + { P_BI_TCXO, 0 }, > > + { P_DISP_CC_PLL0_OUT_MAIN, 1 }, > > + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, > > +}; > > + > > +static const struct clk_parent_data disp_cc_parent_data_5[] = { > > + { .index = DT_BI_TCXO }, > > + { .hw = &disp_cc_pll0.clkr.hw }, > > + { .hw = &disp_cc_pll1.clkr.hw }, > > +}; > > + > > +static const struct parent_map disp_cc_parent_map_6[] = { > > + { P_BI_TCXO, 0 }, > > + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, > > + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, > > +}; > > + > > +static const struct clk_parent_data disp_cc_parent_data_6[] = { > > + { .index = DT_BI_TCXO }, > > + { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, > > + { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, > > +}; > > + > > +static const struct parent_map disp_cc_parent_map_7[] = { > > + { P_BI_TCXO, 0 }, > > + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, > > + /* { P_DISP_CC_PLL1_OUT_EVEN, 5 }, */ > Is this and its .hw below commented out on purpose? If so, why? It's a leftover from dispcc-sm8250, looking closer at this it was introduced by Bjorn in the below commit. 2ebdd326d1995 - clk: qcom: dispcc-sm8250: Add EDP clocks Downstream does have this snippet enabled. https://git.linaro.org/people/robert.foss/linux.git/tree/drivers/clk/qcom/dispcc-lahaina.c?id=5a585e470356af7ab39cbf05274dd9bce9f2f85e#n253 Bjorn: Do you know anything about the snippet being commented out? > > +}; > > + > > +static const struct clk_parent_data disp_cc_parent_data_7[] = { > > + { .index = DT_BI_TCXO }, > > + { .hw = &disp_cc_pll1.clkr.hw }, > > + /* { .hw = &disp_cc_pll1_out_even.clkr.hw }, */ > > +}; > > + > > +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { > > + F(19200000, P_BI_TCXO, 1, 0, 0), > > + F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), > > + F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), > > + { } > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { > > + .cmd_rcgr = 0x22bc, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_3, > > + .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_ahb_clk_src", > > + .parent_data = disp_cc_parent_data_3, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_rcg2_shared_ops, > > + }, > > +}; > > + > > +static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { > > + F(19200000, P_BI_TCXO, 1, 0, 0), > > + { } > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { > > + .cmd_rcgr = 0x210c, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_2, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_byte0_clk_src", > > + .parent_data = disp_cc_parent_data_2, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_byte2_ops, > > + }, > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { > > + .cmd_rcgr = 0x2128, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_2, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_byte1_clk_src", > > + .parent_data = disp_cc_parent_data_2, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_byte2_ops, > > + }, > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = { > > + .cmd_rcgr = 0x223c, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_1, > > + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_dp_aux1_clk_src", > > + .parent_data = disp_cc_parent_data_1, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_rcg2_ops, > > + }, > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { > > + .cmd_rcgr = 0x21d8, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_1, > > + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_dp_aux_clk_src", > > + .parent_data = disp_cc_parent_data_1, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_rcg2_ops, > > + }, > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = { > > + .cmd_rcgr = 0x2208, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_0, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_dp_link1_clk_src", > > + .parent_data = disp_cc_parent_data_0, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > > + .ops = &clk_byte2_ops, > > + }, > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { > > + .cmd_rcgr = 0x2174, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_0, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_dp_link_clk_src", > > + .parent_data = disp_cc_parent_data_0, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > > + .ops = &clk_byte2_ops, > > + }, > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { > > + .cmd_rcgr = 0x21c0, > > + .mnd_width = 16, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_0, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_dp_pixel1_clk_src", > > + .parent_data = disp_cc_parent_data_0, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > > + .ops = &clk_dp_ops, > > + }, > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = { > > + .cmd_rcgr = 0x21f0, > > + .mnd_width = 16, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_0, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_dp_pixel2_clk_src", > > + .parent_data = disp_cc_parent_data_0, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > > + .ops = &clk_dp_ops, > > + }, > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { > > + .cmd_rcgr = 0x21a8, > > + .mnd_width = 16, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_0, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_dp_pixel_clk_src", > > + .parent_data = disp_cc_parent_data_0, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > > + .ops = &clk_dp_ops, > > + }, > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = { > > + .cmd_rcgr = 0x228c, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_1, > > + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_edp_aux_clk_src", > > + .parent_data = disp_cc_parent_data_1, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_rcg2_ops, > > + }, > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src = { > > + .cmd_rcgr = 0x22a4, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_7, > > + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_edp_gtc_clk_src", > > + .parent_data = disp_cc_parent_data_7, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_rcg2_ops, > > + }, > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = { > > + .cmd_rcgr = 0x2270, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_4, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_edp_link_clk_src", > > + .parent_data = disp_cc_parent_data_4, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_byte2_ops, > > + }, > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = { > > + .cmd_rcgr = 0x2258, > > + .mnd_width = 16, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_4, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_edp_pixel_clk_src", > > + .parent_data = disp_cc_parent_data_4, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), > > + .ops = &clk_dp_ops, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_edp_aux_clk = { > > + .halt_reg = 0x2078, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x2078, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_edp_aux_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_edp_aux_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_edp_gtc_clk = { > > + .halt_reg = 0x207c, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x207c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_edp_gtc_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_edp_gtc_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_edp_link_clk = { > > + .halt_reg = 0x2070, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x2070, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_edp_link_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_edp_link_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_edp_link_intf_clk = { > > + .halt_reg = 0x2074, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x2074, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_edp_link_intf_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_edp_link_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_GET_RATE_NOCACHE, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_edp_pixel_clk = { > > + .halt_reg = 0x206c, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x206c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_edp_pixel_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_edp_pixel_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { > > + .cmd_rcgr = 0x2144, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_2, > > + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_esc0_clk_src", > > + .parent_data = disp_cc_parent_data_2, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_rcg2_ops, > > + }, > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { > > + .cmd_rcgr = 0x2160, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_2, > > + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_esc1_clk_src", > > + .parent_data = disp_cc_parent_data_2, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_rcg2_ops, > > + }, > > +}; > > + > > +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { > > + F(19200000, P_BI_TCXO, 1, 0, 0), > > + F(85714286, P_DISP_CC_PLL1_OUT_MAIN, 7, 0, 0), > > + F(100000000, P_DISP_CC_PLL1_OUT_MAIN, 6, 0, 0), > > + F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0), > > + F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), > > + F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), > > + F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), > > + F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), > > + { } > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { > > + .cmd_rcgr = 0x20c4, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_5, > > + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_mdp_clk_src", > > + .parent_data = disp_cc_parent_data_5, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_rcg2_shared_ops, > > + }, > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { > > + .cmd_rcgr = 0x2094, > > + .mnd_width = 8, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_6, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_pclk0_clk_src", > > + .parent_data = disp_cc_parent_data_6, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_pixel_ops, > > + }, > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { > > + .cmd_rcgr = 0x20ac, > > + .mnd_width = 8, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_6, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_pclk1_clk_src", > > + .parent_data = disp_cc_parent_data_6, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_pixel_ops, > > + }, > > +}; > > + > > +static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { > > + F(19200000, P_BI_TCXO, 1, 0, 0), > > + F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), > > + F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), > > + F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), > > + F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), > > + { } > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { > > + .cmd_rcgr = 0x20dc, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_5, > > + .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_rot_clk_src", > > + .parent_data = disp_cc_parent_data_5, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_rcg2_shared_ops, > > + }, > > +}; > > + > > +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { > > + .cmd_rcgr = 0x20f4, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = disp_cc_parent_map_1, > > + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_vsync_clk_src", > > + .parent_data = disp_cc_parent_data_1, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_rcg2_ops, > > + }, > > +}; > > + > > +static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { > > + .reg = 0x2124, > > + .shift = 0, > > + .width = 4, > > + .clkr.hw.init = &(struct clk_init_data) { > > + .name = "disp_cc_mdss_byte0_div_clk_src", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_byte0_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .ops = &clk_regmap_div_ops, > > + }, > > +}; > > + > > +static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { > > + .reg = 0x2140, > > + .shift = 0, > > + .width = 4, > > + .clkr.hw.init = &(struct clk_init_data) { > > + .name = "disp_cc_mdss_byte1_div_clk_src", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_byte1_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .ops = &clk_regmap_div_ops, > > + }, > > +}; > > + > > +static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = { > > + .reg = 0x2220, > > + .shift = 0, > > + .width = 4, > > + .clkr.hw.init = &(struct clk_init_data) { > > + .name = "disp_cc_mdss_dp_link1_div_clk_src", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_dp_link1_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .ops = &clk_regmap_div_ro_ops, > > + }, > > +}; > > + > > +static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = { > > + .reg = 0x218c, > > + .shift = 0, > > + .width = 4, > > + .clkr.hw.init = &(struct clk_init_data) { > > + .name = "disp_cc_mdss_dp_link_div_clk_src", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_dp_link_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .ops = &clk_regmap_div_ro_ops, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_ahb_clk = { > > + .halt_reg = 0x207c, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x207c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_ahb_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_ahb_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_byte0_clk = { > > + .halt_reg = 0x2028, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x2028, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_byte0_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_byte0_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_byte0_intf_clk = { > > + .halt_reg = 0x202c, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x202c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_byte0_intf_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_byte1_clk = { > > + .halt_reg = 0x2030, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x2030, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_byte1_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_byte1_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_byte1_intf_clk = { > > + .halt_reg = 0x2034, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x2034, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_byte1_intf_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_byte1_div_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_dp_aux1_clk = { > > + .halt_reg = 0x2068, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x2068, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_dp_aux1_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_dp_aux1_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_dp_aux_clk = { > > + .halt_reg = 0x2054, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x2054, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_dp_aux_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_dp_aux_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_dp_link1_clk = { > > + .halt_reg = 0x205c, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x205c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_dp_link1_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_dp_link1_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = { > > + .halt_reg = 0x2060, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x2060, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_dp_link1_intf_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_dp_link1_div_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_dp_link_clk = { > > + .halt_reg = 0x2040, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x2040, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_dp_link_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_dp_link_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { > > + .halt_reg = 0x2044, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x2044, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_dp_link_intf_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_dp_pixel1_clk = { > > + .halt_reg = 0x2050, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x2050, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_dp_pixel1_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_dp_pixel2_clk = { > > + .halt_reg = 0x2058, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x2058, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_dp_pixel2_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_dp_pixel2_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_dp_pixel_clk = { > > + .halt_reg = 0x204c, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x204c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_dp_pixel_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_esc0_clk = { > > + .halt_reg = 0x2038, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x2038, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_esc0_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_esc0_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_esc1_clk = { > > + .halt_reg = 0x203c, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x203c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_esc1_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_esc1_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_mdp_clk = { > > + .halt_reg = 0x200c, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x200c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_mdp_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_mdp_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_mdp_lut_clk = { > > + .halt_reg = 0x201c, > > + .halt_check = BRANCH_VOTED, > > + .clkr = { > > + .enable_reg = 0x201c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_mdp_lut_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_mdp_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { > > + .halt_reg = 0x4004, > > + .halt_check = BRANCH_VOTED, > > + .clkr = { > > + .enable_reg = 0x4004, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_non_gdsc_ahb_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_ahb_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_pclk0_clk = { > > + .halt_reg = 0x2004, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x2004, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_pclk0_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_pclk0_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_pclk1_clk = { > > + .halt_reg = 0x2008, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x2008, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_pclk1_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_pclk1_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_rot_clk = { > > + .halt_reg = 0x2014, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x2014, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_rot_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_rot_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { > > + .halt_reg = 0x400c, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x400c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_rscc_ahb_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_ahb_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { > > + .halt_reg = 0x4008, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x4008, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_rscc_vsync_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_vsync_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch disp_cc_mdss_vsync_clk = { > > + .halt_reg = 0x2024, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x2024, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "disp_cc_mdss_vsync_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &disp_cc_mdss_vsync_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct gdsc mdss_gdsc = { > > + .gdscr = 0x3000, > > + .en_rest_wait_val = 0x2, > > + .en_few_wait_val = 0x2, > > + .clk_dis_wait_val = 0xf, > > + .pd = { > > + .name = "mdss_gdsc", > > + }, > > + .pwrsts = PWRSTS_OFF_ON, > > + .flags = HW_CTRL, > > + .supply = "mmcx", > > +}; > > + > > +static struct clk_regmap *disp_cc_sm8350_clocks[] = { > > + [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, > > + [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, > > + [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, > > + [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, > > + [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, > > + [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, > > + [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, > > + [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, > > + [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, > > + [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, > > + [DISP_CC_MDSS_DP_AUX1_CLK] = &disp_cc_mdss_dp_aux1_clk.clkr, > > + [DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr, > > + [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, > > + [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, > > + [DISP_CC_MDSS_DP_LINK1_CLK] = &disp_cc_mdss_dp_link1_clk.clkr, > > + [DISP_CC_MDSS_DP_LINK1_CLK_SRC] = &disp_cc_mdss_dp_link1_clk_src.clkr, > > + [DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = &disp_cc_mdss_dp_link1_div_clk_src.clkr, > > + [DISP_CC_MDSS_DP_LINK1_INTF_CLK] = &disp_cc_mdss_dp_link1_intf_clk.clkr, > > + [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, > > + [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, > > + [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dp_link_div_clk_src.clkr, > > + [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, > > + [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr, > > + [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr, > > + [DISP_CC_MDSS_DP_PIXEL2_CLK] = &disp_cc_mdss_dp_pixel2_clk.clkr, > > + [DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr, > > + [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, > > + [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, > > + [DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr, > > + [DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr, > > + [DISP_CC_MDSS_EDP_GTC_CLK] = &disp_cc_mdss_edp_gtc_clk.clkr, > > + [DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr, > > + [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr, > > + [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr, > > + [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr, > > + [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr, > > + [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr, > > + [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, > > + [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, > > + [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, > > + [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, > > + [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, > > + [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, > > + [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, > > + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, > > + [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, > > + [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, > > + [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, > > + [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, > > + [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, > > + [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, > > + [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, > > + [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, > > + [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, > > + [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, > > + [DISP_CC_PLL0] = &disp_cc_pll0.clkr, > > + [DISP_CC_PLL1] = &disp_cc_pll1.clkr, > > +}; > > + > > +static const struct qcom_reset_map disp_cc_sm8350_resets[] = { > > + [DISP_CC_MDSS_CORE_BCR] = { 0x2000 }, > > + [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 }, > > +}; > > + > > +static struct gdsc *disp_cc_sm8350_gdscs[] = { > > + [MDSS_GDSC] = &mdss_gdsc, > > +}; > > + > > +static const struct regmap_config disp_cc_sm8350_regmap_config = { > > + .reg_bits = 32, > > + .reg_stride = 4, > > + .val_bits = 32, > > + .max_register = 0x10000, > > + .fast_io = true, > > +}; > > + > > +static const struct qcom_cc_desc disp_cc_sm8350_desc = { > > + .config = &disp_cc_sm8350_regmap_config, > > + .clks = disp_cc_sm8350_clocks, > > + .num_clks = ARRAY_SIZE(disp_cc_sm8350_clocks), > > + .resets = disp_cc_sm8350_resets, > > + .num_resets = ARRAY_SIZE(disp_cc_sm8350_resets), > > + .gdscs = disp_cc_sm8350_gdscs, > > + .num_gdscs = ARRAY_SIZE(disp_cc_sm8350_gdscs), > > +}; > > + > > +static const struct of_device_id disp_cc_sm8350_match_table[] = { > > + { .compatible = "qcom,sc8180x-dispcc" }, > > + { .compatible = "qcom,sm8150-dispcc" }, > > + { .compatible = "qcom,sm8350-dispcc" }, > > + { .compatible = "qcom,sm8350-dispcc" }, > > Double 8350 and mis-copied 8180x/8150 D'oh! Thanks for catching this. > > > Konrad > > > + { } > > +}; > > +MODULE_DEVICE_TABLE(of, disp_cc_sm8350_match_table); > > + > > +static void disp_cc_sm8350_pm_runtime_disable(void *data) > > +{ > > + pm_runtime_disable(data); > > +} > > + > > +static int disp_cc_sm8350_probe(struct platform_device *pdev) > > +{ > > + struct regmap *regmap; > > + int ret; > > + > > + pm_runtime_enable(&pdev->dev); > > + > > + ret = devm_add_action_or_reset(&pdev->dev, disp_cc_sm8350_pm_runtime_disable, &pdev->dev); > > + if (ret) > > + return ret; > > + > > + ret = pm_runtime_resume_and_get(&pdev->dev); > > + if (ret) > > + return ret; > > + > > + regmap = qcom_cc_map(pdev, &disp_cc_sm8350_desc); > > + if (IS_ERR(regmap)) { > > + pm_runtime_put(&pdev->dev); > > + return PTR_ERR(regmap); > > + } > > + > > + BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); > > + > > + disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0; > > + > > + disp_cc_pll0_config.config_ctl_hi1_val = 0x2a9a699c; > > + disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000; > > + disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops; > > + disp_cc_pll0.vco_table = lucid_5lpe_vco; > > + disp_cc_pll1_config.config_ctl_hi1_val = 0x2a9a699c; > > + disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000; > > + disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops; > > + disp_cc_pll1.vco_table = lucid_5lpe_vco; > > + > > + clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); > > + clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); > > + > > + /* Enable clock gating for MDP clocks */ > > + regmap_update_bits(regmap, 0x8000, 0x10, 0x10); > > + > > + /* DISP_CC_XO_CLK always-on */ > > + regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); > > + > > + ret = qcom_cc_really_probe(pdev, &disp_cc_sm8350_desc, regmap); > > + > > + pm_runtime_put(&pdev->dev); > > + > > + return ret; > > +} > > + > > +static struct platform_driver disp_cc_sm8350_driver = { > > + .probe = disp_cc_sm8350_probe, > > + .driver = { > > + .name = "disp_cc-sm8350", > > + .of_match_table = disp_cc_sm8350_match_table, > > + }, > > +}; > > + > > +static int __init disp_cc_sm8350_init(void) > > +{ > > + return platform_driver_register(&disp_cc_sm8350_driver); > > +} > > +subsys_initcall(disp_cc_sm8350_init); > > + > > +static void __exit disp_cc_sm8350_exit(void) > > +{ > > + platform_driver_unregister(&disp_cc_sm8350_driver); > > +} > > +module_exit(disp_cc_sm8350_exit); > > + > > +MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver"); > > +MODULE_LICENSE("GPL v2"); ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v5 5/6] dt-bindings: clock: Add Qcom SM8350 DISPCC bindings 2022-06-09 9:29 [PATCH v5 0/6] SM8350 Display/GPU clock enablement Robert Foss ` (3 preceding siblings ...) 2022-06-09 9:29 ` [PATCH v5 4/6] clk: qcom: add support for SM8350 DISPCC Robert Foss @ 2022-06-09 9:29 ` Robert Foss 2022-06-09 9:29 ` [PATCH v5 6/6] arm64: dts: qcom: sm8350: Add DISPCC node Robert Foss 5 siblings, 0 replies; 13+ messages in thread From: Robert Foss @ 2022-06-09 9:29 UTC (permalink / raw) To: agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt, robert.foss, jonathan, linux-arm-msm, linux-clk, devicetree, linux-kernel, Dmitry Baryshkov, Konrad Dybcio Cc: Rob Herring Add sm8350 DISPCC bindings, while these bindings are similar to the sm8x50 bindings, the way clocks are represented has changed in ABI incompatible ways. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> --- Changes since v2 - Add my SoB - Bjorn Changes since v3 - Separate from qcom,dispcc-sm8x50 - Remove clock-names - Make example sm8350 based - Changed author to me due to size of changes Changes since v4 - Add RB - Rob .../bindings/clock/qcom,dispcc-sm8350.yaml | 104 ++++++++++++++++++ .../bindings/clock/qcom,dispcc-sm8x50.yaml | 4 +- .../dt-bindings/clock/qcom,dispcc-sm8350.h | 1 + 3 files changed, 107 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sm8350.yaml create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8350.yaml new file mode 100644 index 000000000000..d7e8739cab32 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8350.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller Binding for SM8350 + +maintainers: + - Robert Foss <robert.foss@linaro.org> + +description: | + Qualcomm display clock control module which supports the clocks, resets and + power domains on SM8350. + + See also: + dt-bindings/clock/qcom,dispcc-sm8350.h + +properties: + compatible: + enum: + - qcom,sm8350-dispcc + + clocks: + items: + - description: Board XO source + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + - description: Link clock from DPTX1 PHY + - description: VCO DIV clock from DPTX1 PHY + - description: Link clock from DPTX2 PHY + - description: VCO DIV clock from DPTX2 PHY + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + - description: Link clock from EDP PHY + - description: VCO DIV clock from EDP PHY + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@af00000 { + compatible = "qcom,sm8350-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&dp_phy 0>, + <&dp_phy 1>, + <&dptx1_phy 0>, + <&dptx1_phy 1>, + <&dptx2_phy 0>, + <&dptx2_phy 1>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <&edp_phy 0>, + <&edp_phy 1>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8350_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 31497677e8de..951fe2ecb7a6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350 maintainers: - Jonathan Marek <jonathan@marek.ca> description: | Qualcomm display clock control module which supports the clocks, resets and - power domains on SM8150 and SM8250. + power domains on SM8150/SM8250. See also: dt-bindings/clock/qcom,dispcc-sm8150.h diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h new file mode 120000 index 000000000000..0312b4544acb --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h @@ -0,0 +1 @@ +qcom,dispcc-sm8250.h \ No newline at end of file -- 2.34.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v5 6/6] arm64: dts: qcom: sm8350: Add DISPCC node 2022-06-09 9:29 [PATCH v5 0/6] SM8350 Display/GPU clock enablement Robert Foss ` (4 preceding siblings ...) 2022-06-09 9:29 ` [PATCH v5 5/6] dt-bindings: clock: Add Qcom SM8350 DISPCC bindings Robert Foss @ 2022-06-09 9:29 ` Robert Foss 5 siblings, 0 replies; 13+ messages in thread From: Robert Foss @ 2022-06-09 9:29 UTC (permalink / raw) To: agross, bjorn.andersson, mturquette, sboyd, robh+dt, krzk+dt, robert.foss, jonathan, linux-arm-msm, linux-clk, devicetree, linux-kernel, Dmitry Baryshkov, Konrad Dybcio Add the dispcc clock-controller DT node for sm8350. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- Changes since v2 - Remove interconnect include - Bjorn Changes since v3 - Switch from .fw_name to .index arch/arm64/boot/dts/qcom/sm8350.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 52428b6df64e..df0f3dd38f0f 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,dispcc-sm8350.h> #include <dt-bindings/clock/qcom,gcc-sm8350.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/dma/qcom-gpi.h> @@ -2525,6 +2526,30 @@ usb_2_dwc3: usb@a800000 { }; }; + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8350-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + power-domains = <&rpmhpd SM8350_MMCX>; + power-domain-names = "mmcx"; + }; + adsp: remoteproc@17300000 { compatible = "qcom,sm8350-adsp-pas"; reg = <0 0x17300000 0 0x100>; -- 2.34.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
end of thread, other threads:[~2022-06-14 21:02 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-06-09 9:29 [PATCH v5 0/6] SM8350 Display/GPU clock enablement Robert Foss 2022-06-09 9:29 ` [PATCH v5 1/6] arm64: dts: qcom: sm8350: Replace integers with rpmpd defines Robert Foss 2022-06-09 9:29 ` [PATCH v5 2/6] clk: qcom: add support for SM8350 GPUCC Robert Foss 2022-06-09 10:55 ` Konrad Dybcio 2022-06-09 11:56 ` Robert Foss 2022-06-09 9:29 ` [PATCH v5 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings Robert Foss 2022-06-11 18:04 ` kernel test robot 2022-06-14 21:01 ` Rob Herring 2022-06-09 9:29 ` [PATCH v5 4/6] clk: qcom: add support for SM8350 DISPCC Robert Foss 2022-06-09 10:52 ` Konrad Dybcio 2022-06-09 12:58 ` Robert Foss 2022-06-09 9:29 ` [PATCH v5 5/6] dt-bindings: clock: Add Qcom SM8350 DISPCC bindings Robert Foss 2022-06-09 9:29 ` [PATCH v5 6/6] arm64: dts: qcom: sm8350: Add DISPCC node Robert Foss
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