From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EFEBC43334 for ; Thu, 16 Jun 2022 12:12:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376845AbiFPMMD (ORCPT ); Thu, 16 Jun 2022 08:12:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233024AbiFPMMC (ORCPT ); Thu, 16 Jun 2022 08:12:02 -0400 Received: from verein.lst.de (verein.lst.de [213.95.11.211]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E44F33B576; Thu, 16 Jun 2022 05:12:01 -0700 (PDT) Received: by verein.lst.de (Postfix, from userid 2407) id 464AD67373; Thu, 16 Jun 2022 14:11:57 +0200 (CEST) Date: Thu, 16 Jun 2022 14:11:57 +0200 From: Christoph Hellwig To: Heiko =?iso-8859-1?Q?St=FCbner?= Cc: Christoph Hellwig , palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, wefu@redhat.com, guoren@kernel.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, samuel@sholland.org, atishp@atishpatra.org, anup@brainfault.org, mick@ics.forth.gr, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org, drew@beagleboard.org, Atish Patra Subject: Re: [PATCH 2/3] riscv: Implement Zicbom-based cache management operations Message-ID: <20220616121157.GA11657@lst.de> References: <20220610004308.1903626-1-heiko@sntech.de> <1752040.TLkxdtWsSY@diego> <20220616115342.GA11289@lst.de> <2041345.KlZ2vcFHjT@diego> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <2041345.KlZ2vcFHjT@diego> User-Agent: Mutt/1.5.17 (2007-11-01) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, Jun 16, 2022 at 02:09:47PM +0200, Heiko Stübner wrote: > My guess was that new platforms implementing cache-management will want > to be non-coherent by default? No. Cache incoherent DMA is absolutely horrible and almost impossible to get right for the corner cases. It is a cost cutting measure seen on cheap SOCs and mostly avoided for more enterprise grade products.