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Fri, 17 Jun 2022 16:11:41 -0700 (PDT) Received: (nullmailer pid 2613068 invoked by uid 1000); Fri, 17 Jun 2022 23:11:39 -0000 Date: Fri, 17 Jun 2022 17:11:39 -0600 From: Rob Herring To: Irui Wang Cc: Hans Verkuil , Mauro Carvalho Chehab , Matthias Brugger , Tzung-Bi Shih , angelogioacchino.delregno@collabora.com, nicolas.dufresne@collabora.com, wenst@chromium.org, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Tomasz Figa , xia.jiang@mediatek.com, maoguang.meng@mediatek.com, kyrie wu , srv_heupstream@mediatek.com Subject: Re: [RESEND V9,1/7] dt-bindings: mediatek: Add mediatek, mt8195-jpgenc compatible Message-ID: <20220617231139.GA2610098-robh@kernel.org> References: <20220614121024.31667-1-irui.wang@mediatek.com> <20220614121024.31667-2-irui.wang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220614121024.31667-2-irui.wang@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Jun 14, 2022 at 08:10:18PM +0800, Irui Wang wrote: > From: kyrie wu > > Add mediatek,mt8195-jpgenc compatible to binding document. > > Signed-off-by: kyrie wu > --- > .../media/mediatek,mt8195-jpegenc.yaml | 153 ++++++++++++++++++ > 1 file changed, 153 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml > new file mode 100644 > index 000000000000..a7f9f723d5db > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml > @@ -0,0 +1,153 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek JPEG Encoder Device Tree Bindings > + > +maintainers: > + - kyrie wu > + > +description: |- > + MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs > + > +properties: > + compatible: > + items: > + - const: mediatek,mt8195-jpgenc > + > + mediatek,jpegenc-multi-core: > + type: boolean > + description: | > + Indicates whether the jpeg encoder has multiple cores or not. > + > + power-domains: > + maxItems: 1 > + > + iommus: > + maxItems: 4 > + description: | > + Points to the respective IOMMU block with master port as argument, see > + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. > + Ports are according to the HW. > + > + "#address-cells": > + const: 2 > + > + "#size-cells": > + const: 2 > + > + ranges: true > + > +# Required child node: > +patternProperties: > + "^jpgenc@[0-9a-f]+$": > + type: object > + description: | > + The jpeg encoder hardware device node which should be added as subnodes to > + the main jpeg node. > + > + properties: > + compatible: > + const: mediatek,mt8195-jpgenc-hw > + > + reg: > + maxItems: 1 > + > + hw_id: > + description: | > + Current jpegenc hw id. Same question here. Surely, I asked sometime in the last 8 versions, but no explanation here and I'm not going to go look for it. > + > + iommus: > + minItems: 1 > + maxItems: 32 > + description: | > + List of the hardware port in respective IOMMU block for current Socs. > + Refer to bindings/iommu/mediatek,iommu.yaml. > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + items: > + - const: jpgenc > + > + power-domains: > + maxItems: 1 > + > + required: > + - compatible > + - reg > + - hw_id > + - iommus > + - interrupts > + - clocks > + - clock-names > + - power-domains > + > + additionalProperties: false > + > +required: > + - compatible > + - power-domains > + - iommus > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + jpgenc_master { > + compatible = "mediatek,mt8195-jpgenc"; > + mediatek,jpegenc-multi-core; > + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; > + iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, > + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, > + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, > + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + jpgenc@1a030000 { > + compatible = "mediatek,mt8195-jpgenc-hw"; > + reg = <0 0x1a030000 0 0x10000>; > + hw_id = <0>; > + iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, > + <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, > + <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, > + <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; > + interrupts = ; > + clocks = <&vencsys CLK_VENC_JPGENC>; > + clock-names = "jpgenc"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; > + }; > + > + jpgenc@1b030000 { > + compatible = "mediatek,mt8195-jpgenc-hw"; > + reg = <0 0x1b030000 0 0x10000>; > + hw_id = <1>; > + iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, > + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, > + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, > + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; > + interrupts = ; > + clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; > + clock-names = "jpgenc"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; > + }; > + }; > + }; > -- > 2.18.0 > >