From: Robert Marko <robimarko@gmail.com>
To: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com,
vkoul@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org,
linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org
Cc: Robert Marko <robimarko@gmail.com>
Subject: [PATCH v3 1/3] phy: qcom-qmp-pcie: make pipe clock rate configurable
Date: Tue, 21 Jun 2022 21:30:18 +0200 [thread overview]
Message-ID: <20220621193020.1630180-1-robimarko@gmail.com> (raw)
IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz
like every other PCIe QMP PHY does, so make it configurable as part of the
qmp_phy_cfg.
Set all of the current configs to use 125MHz as currently done.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 28 ++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index b2cd0cf965d8..4dc4d4f8547e 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -1284,6 +1284,9 @@ struct qmp_phy_cfg {
/* true, if PHY has secondary tx/rx lanes to be configured */
bool is_dual_lane_phy;
+
+ /* QMP PHY pipe clock interface rate */
+ unsigned long pipe_clock_rate;
};
/**
@@ -1419,6 +1422,8 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
+
+ .pipe_clock_rate = 125000000,
};
static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
@@ -1447,6 +1452,8 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
+
+ .pipe_clock_rate = 125000000,
};
static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
@@ -1478,6 +1485,8 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
+
+ .pipe_clock_rate = 125000000,
};
static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
@@ -1507,6 +1516,8 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
+
+ .pipe_clock_rate = 125000000,
};
static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
@@ -1546,6 +1557,8 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
+
+ .pipe_clock_rate = 125000000,
};
static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
@@ -1586,6 +1599,8 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
+
+ .pipe_clock_rate = 125000000,
};
static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
@@ -1611,6 +1626,8 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
.phy_status = PHYSTATUS,
+
+ .pipe_clock_rate = 125000000,
};
static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
@@ -1641,6 +1658,8 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
+
+ .pipe_clock_rate = 125000000,
};
static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
@@ -1673,6 +1692,8 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
+
+ .pipe_clock_rate = 125000000,
};
static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
@@ -1704,6 +1725,8 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
+
+ .pipe_clock_rate = 125000000,
};
static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
@@ -1736,6 +1759,8 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
.has_pwrdn_delay = true,
.pwrdn_delay_min = 995, /* us */
.pwrdn_delay_max = 1005, /* us */
+
+ .pipe_clock_rate = 125000000,
};
static void qcom_qmp_phy_pcie_configure_lane(void __iomem *base,
@@ -2121,8 +2146,7 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
init.ops = &clk_fixed_rate_ops;
- /* controllers using QMP phys use 125MHz pipe clock interface */
- fixed->fixed_rate = 125000000;
+ fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate;
fixed->hw.init = &init;
ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
--
2.36.1
next reply other threads:[~2022-06-21 19:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-21 19:30 Robert Marko [this message]
2022-06-21 19:30 ` [PATCH v3 2/3] dt-bindings: phy: qcom,qmp: add IPQ8074 PCIe Gen3 PHY binding Robert Marko
2022-06-21 19:30 ` [PATCH v3 3/3] phy: qcom-qmp-pcie: add IPQ8074 PCIe Gen3 QMP PHY support Robert Marko
2022-06-21 19:33 ` Dmitry Baryshkov
2022-06-21 19:32 ` [PATCH v3 1/3] phy: qcom-qmp-pcie: make pipe clock rate configurable Dmitry Baryshkov
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