From: Jayesh Choudhary <j-choudhary@ti.com>
To: <devicetree@vger.kernel.org>
Cc: <nm@ti.com>, <vigneshr@ti.com>, <kristo@kernel.org>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<j-choudhary@ti.com>, <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH] arm64: dts: ti: k3-am62-main: Enable crypto accelerator
Date: Thu, 23 Jun 2022 15:29:55 +0530 [thread overview]
Message-ID: <20220623095955.161307-1-j-choudhary@ti.com> (raw)
Add the node for sa3ul crypto accelerator.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
On local testing, crypto self-tests and tcrypt tests were passing
for SHA256, SHA512, ECB-AES and CBC-AES algorithms.
RNG node has not been added due to the indirect access of the
hardware random number generator from OP-TEE.
arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
index df3b9883e887..30bd22ff2fc9 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
@@ -165,6 +165,19 @@
};
};
+ crypto: crypto@40900000 {
+ compatible = "ti,am62-sa3ul";
+ reg = <0x00 0x40900000 0x00 0x1200>;
+ power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
+
+ dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
+ <&main_pktdma 0x7507 0>;
+ dma-names = "tx", "rx1", "rx2";
+ };
+
main_pmx0: pinctrl@f4000 {
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
--
2.17.1
next reply other threads:[~2022-06-23 10:00 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-23 9:59 Jayesh Choudhary [this message]
2022-06-23 18:21 ` [PATCH] arm64: dts: ti: k3-am62-main: Enable crypto accelerator Andrew Davis
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