From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Stephen Boyd <swboyd@chromium.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Taniya Das <quic_tdas@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [PATCH 03/15] clk: qcom: gcc-msm8960: use ARRAY_SIZE instead of specifying num_parents
Date: Thu, 23 Jun 2022 15:04:06 +0300 [thread overview]
Message-ID: <20220623120418.250589-4-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20220623120418.250589-1-dmitry.baryshkov@linaro.org>
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-msm8960.c | 96 +++++++++++++++++-----------------
1 file changed, 48 insertions(+), 48 deletions(-)
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index a6e13b91e4c8..cf1bccab2fa5 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -349,7 +349,7 @@ static struct clk_rcg gsbi1_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -400,7 +400,7 @@ static struct clk_rcg gsbi2_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -451,7 +451,7 @@ static struct clk_rcg gsbi3_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi3_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -502,7 +502,7 @@ static struct clk_rcg gsbi4_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -553,7 +553,7 @@ static struct clk_rcg gsbi5_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -604,7 +604,7 @@ static struct clk_rcg gsbi6_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi6_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -655,7 +655,7 @@ static struct clk_rcg gsbi7_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi7_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -706,7 +706,7 @@ static struct clk_rcg gsbi8_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi8_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -755,7 +755,7 @@ static struct clk_rcg gsbi9_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi9_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -804,7 +804,7 @@ static struct clk_rcg gsbi10_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi10_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -853,7 +853,7 @@ static struct clk_rcg gsbi11_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi11_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -902,7 +902,7 @@ static struct clk_rcg gsbi12_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi12_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -964,7 +964,7 @@ static struct clk_rcg gsbi1_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1013,7 +1013,7 @@ static struct clk_rcg gsbi2_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1062,7 +1062,7 @@ static struct clk_rcg gsbi3_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi3_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1111,7 +1111,7 @@ static struct clk_rcg gsbi4_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1160,7 +1160,7 @@ static struct clk_rcg gsbi5_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1209,7 +1209,7 @@ static struct clk_rcg gsbi6_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi6_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1258,7 +1258,7 @@ static struct clk_rcg gsbi7_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi7_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1307,7 +1307,7 @@ static struct clk_rcg gsbi8_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi8_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1356,7 +1356,7 @@ static struct clk_rcg gsbi9_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi9_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1405,7 +1405,7 @@ static struct clk_rcg gsbi10_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi10_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1454,7 +1454,7 @@ static struct clk_rcg gsbi11_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi11_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1503,7 +1503,7 @@ static struct clk_rcg gsbi12_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi12_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1565,7 +1565,7 @@ static struct clk_rcg gp0_src = {
.hw.init = &(struct clk_init_data){
.name = "gp0_src",
.parent_names = gcc_pxo_pll8_cxo,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1614,7 +1614,7 @@ static struct clk_rcg gp1_src = {
.hw.init = &(struct clk_init_data){
.name = "gp1_src",
.parent_names = gcc_pxo_pll8_cxo,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1663,7 +1663,7 @@ static struct clk_rcg gp2_src = {
.hw.init = &(struct clk_init_data){
.name = "gp2_src",
.parent_names = gcc_pxo_pll8_cxo,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1715,7 +1715,7 @@ static struct clk_rcg prng_src = {
.hw.init = &(struct clk_init_data){
.name = "prng_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
},
@@ -1777,7 +1777,7 @@ static struct clk_rcg sdc1_src = {
.hw.init = &(struct clk_init_data){
.name = "sdc1_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -1825,7 +1825,7 @@ static struct clk_rcg sdc2_src = {
.hw.init = &(struct clk_init_data){
.name = "sdc2_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -1873,7 +1873,7 @@ static struct clk_rcg sdc3_src = {
.hw.init = &(struct clk_init_data){
.name = "sdc3_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -1921,7 +1921,7 @@ static struct clk_rcg sdc4_src = {
.hw.init = &(struct clk_init_data){
.name = "sdc4_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -1969,7 +1969,7 @@ static struct clk_rcg sdc5_src = {
.hw.init = &(struct clk_init_data){
.name = "sdc5_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -2022,7 +2022,7 @@ static struct clk_rcg tsif_ref_src = {
.hw.init = &(struct clk_init_data){
.name = "tsif_ref_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2076,7 +2076,7 @@ static struct clk_rcg usb_hs1_xcvr_src = {
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2125,7 +2125,7 @@ static struct clk_rcg usb_hs3_xcvr_src = {
.hw.init = &(struct clk_init_data){
.name = "usb_hs3_xcvr_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2174,7 +2174,7 @@ static struct clk_rcg usb_hs4_xcvr_src = {
.hw.init = &(struct clk_init_data){
.name = "usb_hs4_xcvr_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2223,7 +2223,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = {
.hw.init = &(struct clk_init_data){
.name = "usb_hsic_xcvr_fs_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2241,7 +2241,7 @@ static struct clk_branch usb_hsic_xcvr_fs_clk = {
.hw.init = &(struct clk_init_data){
.name = "usb_hsic_xcvr_fs_clk",
.parent_names = usb_hsic_xcvr_fs_src_p,
- .num_parents = 1,
+ .num_parents = ARRAY_SIZE(usb_hsic_xcvr_fs_src_p),
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -2256,7 +2256,7 @@ static struct clk_branch usb_hsic_system_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.parent_names = usb_hsic_xcvr_fs_src_p,
- .num_parents = 1,
+ .num_parents = ARRAY_SIZE(usb_hsic_xcvr_fs_src_p),
.name = "usb_hsic_system_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -2318,7 +2318,7 @@ static struct clk_rcg usb_fs1_xcvr_fs_src = {
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_fs_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2336,7 +2336,7 @@ static struct clk_branch usb_fs1_xcvr_fs_clk = {
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_fs_clk",
.parent_names = usb_fs1_xcvr_fs_src_p,
- .num_parents = 1,
+ .num_parents = ARRAY_SIZE(usb_fs1_xcvr_fs_src_p),
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -2351,7 +2351,7 @@ static struct clk_branch usb_fs1_system_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.parent_names = usb_fs1_xcvr_fs_src_p,
- .num_parents = 1,
+ .num_parents = ARRAY_SIZE(usb_fs1_xcvr_fs_src_p),
.name = "usb_fs1_system_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -2385,7 +2385,7 @@ static struct clk_rcg usb_fs2_xcvr_fs_src = {
.hw.init = &(struct clk_init_data){
.name = "usb_fs2_xcvr_fs_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2403,7 +2403,7 @@ static struct clk_branch usb_fs2_xcvr_fs_clk = {
.hw.init = &(struct clk_init_data){
.name = "usb_fs2_xcvr_fs_clk",
.parent_names = usb_fs2_xcvr_fs_src_p,
- .num_parents = 1,
+ .num_parents = ARRAY_SIZE(usb_fs2_xcvr_fs_src_p),
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -2419,7 +2419,7 @@ static struct clk_branch usb_fs2_system_clk = {
.hw.init = &(struct clk_init_data){
.name = "usb_fs2_system_clk",
.parent_names = usb_fs2_xcvr_fs_src_p,
- .num_parents = 1,
+ .num_parents = ARRAY_SIZE(usb_fs2_xcvr_fs_src_p),
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -2873,7 +2873,7 @@ static struct clk_rcg ce3_src = {
.hw.init = &(struct clk_init_data){
.name = "ce3_src",
.parent_names = gcc_pxo_pll8_pll3,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2935,7 +2935,7 @@ static struct clk_rcg sata_clk_src = {
.hw.init = &(struct clk_init_data){
.name = "sata_clk_src",
.parent_names = gcc_pxo_pll8_pll3,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
--
2.35.1
next prev parent reply other threads:[~2022-06-23 12:04 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-23 12:04 [PATCH 00/15] clk: qcom: use parent_hws/_data for APQ8064 clocks Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 01/15] dt-bindings: clocks: qcom,gcc-apq8064: define clocks/-names properties Dmitry Baryshkov
2022-06-24 15:56 ` Krzysztof Kozlowski
2022-06-23 12:04 ` [PATCH 02/15] dt-bindings: clocks: qcom,mmcc: define clocks/clock-names for MSM8960 Dmitry Baryshkov
2022-06-24 15:57 ` Krzysztof Kozlowski
2022-06-25 0:00 ` Dmitry Baryshkov
2022-08-30 7:17 ` Dmitry Baryshkov
2022-08-30 14:56 ` Krzysztof Kozlowski
2022-06-23 12:04 ` Dmitry Baryshkov [this message]
2022-06-23 12:04 ` [PATCH 04/15] clk: qcom: gcc-msm8960: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 05/15] clk: qcom: lcc-msm8960: use macros to implement mi2s clocks Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 06/15] clk: qcom: lcc-msm8960: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 07/15] clk: qcom: mmcc-msm8960: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 08/15] clk: qcom: mmcc-msm8960: move clock parent tables down Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 09/15] clk: qcom: mmcc-msm8960: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 10/15] ARM: dts: qcom: apq8064: add clocks to the LCC device node Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 11/15] ARM: dts: qcom: msm8960: " Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 12/15] ARM: dts: qcom: apq8064: add clocks to the GCC " Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 13/15] ARM: dts: qcom: msm8960: " Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 14/15] ARM: dts: qcom: apq8064: add clocks to the MMCC " Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 15/15] ARM: dts: qcom: msm8960: " Dmitry Baryshkov
2022-07-04 20:14 ` [PATCH 00/15] clk: qcom: use parent_hws/_data for APQ8064 clocks David Heidelberg
2022-09-09 10:16 ` Dmitry Baryshkov
2022-09-15 3:36 ` (subset) " Bjorn Andersson
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