From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Stephen Boyd <swboyd@chromium.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Taniya Das <quic_tdas@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [PATCH 06/15] clk: qcom: lcc-msm8960: use parent_hws/_data instead of parent_names
Date: Thu, 23 Jun 2022 15:04:09 +0300 [thread overview]
Message-ID: <20220623120418.250589-7-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20220623120418.250589-1-dmitry.baryshkov@linaro.org>
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/lcc-msm8960.c | 69 ++++++++++++++++++----------------
1 file changed, 37 insertions(+), 32 deletions(-)
diff --git a/drivers/clk/qcom/lcc-msm8960.c b/drivers/clk/qcom/lcc-msm8960.c
index 99a3d2d486b4..3926184cc91b 100644
--- a/drivers/clk/qcom/lcc-msm8960.c
+++ b/drivers/clk/qcom/lcc-msm8960.c
@@ -33,7 +33,9 @@ static struct clk_pll pll4 = {
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll4",
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "pxo", .name = "pxo_board" },
+ },
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -49,9 +51,9 @@ static const struct parent_map lcc_pxo_pll4_map[] = {
{ P_PLL4, 2 }
};
-static const char * const lcc_pxo_pll4[] = {
- "pxo",
- "pll4_vote",
+static const struct clk_parent_data lcc_pxo_pll4[] = {
+ { .fw_name = "pxo", .name = "pxo_board" },
+ { .fw_name = "pll4_vote", .name = "pll4_vote" },
};
static struct freq_tbl clk_tbl_aif_osr_492[] = {
@@ -112,17 +114,13 @@ static struct clk_rcg prefix##_osr_src = { \
.enable_mask = BIT(9), \
.hw.init = &(struct clk_init_data){ \
.name = #prefix "_osr_src", \
- .parent_names = lcc_pxo_pll4, \
- .num_parents = 2, \
+ .parent_data = lcc_pxo_pll4, \
+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), \
.ops = &clk_rcg_ops, \
.flags = CLK_SET_RATE_GATE, \
}, \
}, \
}; \
- \
-static const char * const lcc_##prefix##_parents[] = { \
- #prefix "_osr_src", \
-}; \
#define CLK_AIF_OSR_CLK(prefix, _ns, hr, en_bit) \
static struct clk_branch prefix##_osr_clk = { \
@@ -134,7 +132,9 @@ static struct clk_branch prefix##_osr_clk = { \
.enable_mask = BIT(en_bit), \
.hw.init = &(struct clk_init_data){ \
.name = #prefix "_osr_clk", \
- .parent_names = lcc_##prefix##_parents, \
+ .parent_hws = (const struct clk_hw*[]){ \
+ &prefix##_osr_src.clkr.hw, \
+ }, \
.num_parents = 1, \
.ops = &clk_branch_ops, \
.flags = CLK_SET_RATE_PARENT, \
@@ -150,7 +150,9 @@ static struct clk_regmap_div prefix##_div_clk = { \
.clkr = { \
.hw.init = &(struct clk_init_data){ \
.name = #prefix "_div_clk", \
- .parent_names = lcc_##prefix##_parents, \
+ .parent_hws = (const struct clk_hw*[]){ \
+ &prefix##_osr_src.clkr.hw, \
+ }, \
.num_parents = 1, \
.ops = &clk_regmap_div_ops, \
}, \
@@ -167,9 +169,9 @@ static struct clk_branch prefix##_bit_div_clk = { \
.enable_mask = BIT(en_bit), \
.hw.init = &(struct clk_init_data){ \
.name = #prefix "_bit_div_clk", \
- .parent_names = (const char *[]){ \
- #prefix "_div_clk" \
- }, \
+ .parent_hws = (const struct clk_hw*[]){ \
+ &prefix##_div_clk.clkr.hw, \
+ }, \
.num_parents = 1, \
.ops = &clk_branch_ops, \
.flags = CLK_SET_RATE_PARENT, \
@@ -185,9 +187,10 @@ static struct clk_regmap_mux prefix##_bit_clk = { \
.clkr = { \
.hw.init = &(struct clk_init_data){ \
.name = #prefix "_bit_clk", \
- .parent_names = (const char *[]){ \
- #prefix "_bit_div_clk", \
- #prefix "_codec_clk", \
+ .parent_data = (const struct clk_parent_data[]){ \
+ { .hw = &prefix##_bit_div_clk.clkr.hw, }, \
+ { .fw_name = #prefix "_codec_clk", \
+ .name = #prefix "_codec_clk", }, \
}, \
.num_parents = 2, \
.ops = &clk_regmap_mux_closest_ops, \
@@ -273,8 +276,8 @@ static struct clk_rcg pcm_src = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "pcm_src",
- .parent_names = lcc_pxo_pll4,
- .num_parents = 2,
+ .parent_data = lcc_pxo_pll4,
+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -290,7 +293,9 @@ static struct clk_branch pcm_clk_out = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "pcm_clk_out",
- .parent_names = (const char *[]){ "pcm_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &pcm_src.clkr.hw
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -305,9 +310,9 @@ static struct clk_regmap_mux pcm_clk = {
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "pcm_clk",
- .parent_names = (const char *[]){
- "pcm_clk_out",
- "pcm_codec_clk",
+ .parent_data = (const struct clk_parent_data[]){
+ { .hw = &pcm_clk_out.clkr.hw },
+ { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" },
},
.num_parents = 2,
.ops = &clk_regmap_mux_closest_ops,
@@ -341,18 +346,14 @@ static struct clk_rcg slimbus_src = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "slimbus_src",
- .parent_names = lcc_pxo_pll4,
- .num_parents = 2,
+ .parent_data = lcc_pxo_pll4,
+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
-static const char * const lcc_slimbus_parents[] = {
- "slimbus_src",
-};
-
static struct clk_branch audio_slimbus_clk = {
.halt_reg = 0xd4,
.halt_bit = 0,
@@ -362,7 +363,9 @@ static struct clk_branch audio_slimbus_clk = {
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "audio_slimbus_clk",
- .parent_names = lcc_slimbus_parents,
+ .parent_hws = (const struct clk_hw*[]){
+ &slimbus_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -379,7 +382,9 @@ static struct clk_branch sps_slimbus_clk = {
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "sps_slimbus_clk",
- .parent_names = lcc_slimbus_parents,
+ .parent_hws = (const struct clk_hw*[]){
+ &slimbus_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
--
2.35.1
next prev parent reply other threads:[~2022-06-23 12:04 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-23 12:04 [PATCH 00/15] clk: qcom: use parent_hws/_data for APQ8064 clocks Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 01/15] dt-bindings: clocks: qcom,gcc-apq8064: define clocks/-names properties Dmitry Baryshkov
2022-06-24 15:56 ` Krzysztof Kozlowski
2022-06-23 12:04 ` [PATCH 02/15] dt-bindings: clocks: qcom,mmcc: define clocks/clock-names for MSM8960 Dmitry Baryshkov
2022-06-24 15:57 ` Krzysztof Kozlowski
2022-06-25 0:00 ` Dmitry Baryshkov
2022-08-30 7:17 ` Dmitry Baryshkov
2022-08-30 14:56 ` Krzysztof Kozlowski
2022-06-23 12:04 ` [PATCH 03/15] clk: qcom: gcc-msm8960: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 04/15] clk: qcom: gcc-msm8960: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 05/15] clk: qcom: lcc-msm8960: use macros to implement mi2s clocks Dmitry Baryshkov
2022-06-23 12:04 ` Dmitry Baryshkov [this message]
2022-06-23 12:04 ` [PATCH 07/15] clk: qcom: mmcc-msm8960: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 08/15] clk: qcom: mmcc-msm8960: move clock parent tables down Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 09/15] clk: qcom: mmcc-msm8960: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 10/15] ARM: dts: qcom: apq8064: add clocks to the LCC device node Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 11/15] ARM: dts: qcom: msm8960: " Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 12/15] ARM: dts: qcom: apq8064: add clocks to the GCC " Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 13/15] ARM: dts: qcom: msm8960: " Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 14/15] ARM: dts: qcom: apq8064: add clocks to the MMCC " Dmitry Baryshkov
2022-06-23 12:04 ` [PATCH 15/15] ARM: dts: qcom: msm8960: " Dmitry Baryshkov
2022-07-04 20:14 ` [PATCH 00/15] clk: qcom: use parent_hws/_data for APQ8064 clocks David Heidelberg
2022-09-09 10:16 ` Dmitry Baryshkov
2022-09-15 3:36 ` (subset) " Bjorn Andersson
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