From: Rahul T R <r-ravikumar@ti.com>
To: <linux-phy@lists.infradead.org>, <kishon@ti.com>,
<vkoul@kernel.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>
Cc: <p.yadav@ti.com>, <tomi.valkeinen@ideasonboard.com>,
<laurent.pinchart@ideasonboard.com>,
<linux-kernel@vger.kernel.org>, <jpawar@cadence.com>,
<sjakhade@cadence.com>, <mparab@cadence.com>,
<devicetree@vger.kernel.org>, <vigneshr@ti.com>,
<lee.jones@linaro.org>, Rahul T R <r-ravikumar@ti.com>
Subject: [PATCH v4 2/3] phy: cdns-dphy: Add band config for dphy tx
Date: Thu, 23 Jun 2022 18:24:32 +0530 [thread overview]
Message-ID: <20220623125433.18467-3-r-ravikumar@ti.com> (raw)
In-Reply-To: <20220623125433.18467-1-r-ravikumar@ti.com>
Add support for band ctrl config for dphy tx.
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
---
drivers/phy/cadence/cdns-dphy.c | 40 ++++++++++++++++++++++++++++++++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c
index ba042e39cfaf..14f951013b4f 100644
--- a/drivers/phy/cadence/cdns-dphy.c
+++ b/drivers/phy/cadence/cdns-dphy.c
@@ -3,6 +3,7 @@
* Copyright: 2017-2018 Cadence Design Systems, Inc.
*/
+#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/io.h>
@@ -45,6 +46,10 @@
#define DPHY_CMN_OPDIV_FROM_REG BIT(6)
#define DPHY_CMN_OPDIV(x) ((x) << 7)
+#define DPHY_BAND_CFG DPHY_PCS(0x0)
+#define DPHY_BAND_CFG_LEFT_BAND GENMASK(4, 0)
+#define DPHY_BAND_CFG_RIGHT_BAND GENMASK(9, 5)
+
#define DPHY_PSM_CFG DPHY_PCS(0x4)
#define DPHY_PSM_CFG_FROM_REG BIT(0)
#define DPHY_PSM_CLK_DIV(x) ((x) << 1)
@@ -92,6 +97,12 @@ struct cdns_dphy {
struct phy *phy;
};
+/* Order of bands is important since the index is the band number. */
+static const unsigned int tx_bands[] = {
+ 80, 100, 120, 160, 200, 240, 320, 390, 450, 510, 560, 640, 690, 770,
+ 870, 950, 1000, 1200, 1400, 1600, 1800, 2000, 2200, 2500
+};
+
static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy,
struct cdns_dphy_cfg *cfg,
struct phy_configure_opts_mipi_dphy *opts,
@@ -232,6 +243,24 @@ static int cdns_dphy_config_from_opts(struct phy *phy,
return 0;
}
+static int cdns_dphy_tx_get_band_ctrl(unsigned long hs_clk_rate)
+{
+ unsigned int rate;
+ int i;
+
+ rate = hs_clk_rate / 1000000UL;
+
+ if (rate < tx_bands[0])
+ return -EOPNOTSUPP;
+
+ for (i = 0; i < ARRAY_SIZE(tx_bands) - 1; i++) {
+ if (rate >= tx_bands[i] && rate < tx_bands[i + 1])
+ return i;
+ }
+
+ return -EOPNOTSUPP;
+}
+
static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode,
union phy_configure_opts *opts)
{
@@ -247,7 +276,8 @@ static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
{
struct cdns_dphy *dphy = phy_get_drvdata(phy);
struct cdns_dphy_cfg cfg = { 0 };
- int ret;
+ int ret, band_ctrl;
+ unsigned int reg;
ret = cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);
if (ret)
@@ -276,6 +306,14 @@ static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
*/
cdns_dphy_set_pll_cfg(dphy, &cfg);
+ band_ctrl = cdns_dphy_tx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate);
+ if (band_ctrl < 0)
+ return band_ctrl;
+
+ reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) |
+ FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl);
+ writel(reg, dphy->regs + DPHY_BAND_CFG);
+
return 0;
}
--
2.36.1
next prev parent reply other threads:[~2022-06-23 12:56 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-23 12:54 [PATCH v4 0/3] Add support for dphy tx on j721e Rahul T R
2022-06-23 12:54 ` [PATCH v4 1/3] phy: dt-bindings: cdns,dphy: Add compatible for dphy " Rahul T R
2022-06-23 12:54 ` Rahul T R [this message]
2022-06-23 12:54 ` [PATCH v4 3/3] phy: cdns-dphy: Add support for DPHY TX on J721e Rahul T R
2022-06-24 9:45 ` Pratyush Yadav
2022-07-05 6:53 ` [PATCH v4 0/3] Add support for dphy tx on j721e Vinod Koul
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