[PATCH v2 08/10] iio: adc: mcp3911: add support for phase

Marcus Folkesson
2022-06-25T10:37:35Z

The MCP3911 incorporates a phase delay generator,
which ensures that the two ADCs are converting the
inputs with a fixed delay between them.
Expose it to userspace.

Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
---

Notes:
v2:
- Fix formatting (Andy Schevchenko)

drivers/iio/adc/mcp3911.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/iio/adc/mcp3911.c b/drivers/iio/adc/mcp3911.c
index ede1ad97ed4d..a0609d7663e1 100644
--- a/drivers/iio/adc/mcp3911.c
+++ b/drivers/iio/adc/mcp3911.c
@@ -155,6 +155,17 @@ static int mcp3911_read_raw(struct iio_dev *indio_dev,

ret = IIO_VAL_INT;
break;
+
+ case IIO_CHAN_INFO_PHASE:
+ ret = mcp3911_read(adc,
+ MCP3911_REG_PHASE, val, 2);
+ if (ret)
+ goto out;
+
+ *val = sign_extend32(*val, 12);
+ ret = IIO_VAL_INT;
+ break;
+
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
ret = mcp3911_read(adc,
MCP3911_REG_CONFIG, val, 2);
@@ -225,6 +236,15 @@ static int mcp3911_write_raw(struct iio_dev *indio_dev,
MCP3911_STATUSCOM_EN_OFFCAL, 2);
break;

+ case IIO_CHAN_INFO_PHASE:
+ if (val2 != 0 || val > 0xfff) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ /* Write phase */
+ ret = mcp3911_write(adc, MCP3911_REG_PHASE, val, 2);
+ break;
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
for (int i = 0; i < sizeof(mcp3911_osr_table); i++) {
if (val == mcp3911_osr_table[i]) {
@@ -248,7 +268,9 @@ static int mcp3911_write_raw(struct iio_dev *indio_dev,
.channel = idx, \
.scan_index = idx, \
.scan_index = idx, \
- .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
+ .info_mask_shared_by_type = \
+ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO)| \
+ BIT(IIO_CHAN_INFO_PHASE), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_OFFSET) | \
BIT(IIO_CHAN_INFO_SCALE), \
--
2.36.1