From: Sudeep Holla <sudeep.holla@arm.com>
To: Conor Dooley <conor@kernel.org>
Cc: Daire McNamara <daire.mcnamara@microchip.com>,
Ivan Griffin <ivan.griffin@microchip.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Palmer Dabbelt <palmer@rivosinc.com>,
linux-riscv@lists.infradead.org,
Conor Dooley <conor.dooley@microchip.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Atish Patra <atishp@atishpatra.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] riscv: dts: microchip: hook up the mpfs' l2cache
Date: Thu, 30 Jun 2022 16:41:32 +0100 [thread overview]
Message-ID: <20220630154132.i54to4l4divkbr2d@bogus> (raw)
In-Reply-To: <20220629200732.4039258-1-conor@kernel.org>
On Wed, Jun 29, 2022 at 09:07:33PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The initial PolarFire SoC devicetree must have been forked off from
> the fu540 one prior to the addition of l2cache controller support being
> added there. When the controller node was added to mpfs.dtsi, it was
> not hooked up to the CPUs & thus sysfs reports an incorrect cache
> configuration. Hook it up.
>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
--
Regards,
Sudeep
next prev parent reply other threads:[~2022-06-30 15:42 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-29 20:07 [PATCH] riscv: dts: microchip: hook up the mpfs' l2cache Conor Dooley
2022-06-30 15:41 ` Sudeep Holla [this message]
2022-07-05 11:42 ` [PATCH] riscv: dts: microchip: hook up the mpfs's l2cache Daire McNamara
2022-07-05 16:36 ` [PATCH] riscv: dts: microchip: hook up the mpfs' l2cache Conor Dooley
2022-07-15 17:32 ` Palmer Dabbelt
2022-07-15 17:38 ` Conor.Dooley
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