From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB440C433EF for ; Fri, 1 Jul 2022 15:29:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231320AbiGAP3J (ORCPT ); Fri, 1 Jul 2022 11:29:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229503AbiGAP3H (ORCPT ); Fri, 1 Jul 2022 11:29:07 -0400 Received: from mail-io1-f52.google.com (mail-io1-f52.google.com [209.85.166.52]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABF7D2558A; Fri, 1 Jul 2022 08:29:06 -0700 (PDT) Received: by mail-io1-f52.google.com with SMTP id y2so2561559ior.12; Fri, 01 Jul 2022 08:29:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=Ub5AkERHAhUeuVteOCgF0rqWbNQPzRgAJcYvL2d8G34=; b=PBJytlizWK5Sgz/El55dRpH1Skv2umq9DjgZbsmlZYUJrOmAv+3Ku79z2/ssBrkwGk 2inLiBHW3wuCVWuHF2VYFo0wYGC3qsZCt0H9sRE6sVaNz8XR6pxHCm059RiaPKMQYkG0 P4P0LHxCKCLWC/C8qGo8dFS14IOdY+JzTzJaeSUoV4nrGMBPT0COeK17Fqfek6p9tf/x 1i9FQxQIv6NIm+Npv7TV+E+lTRQmrS8OHsALidDJF+OE7JagRgoAAQ4kqegXzTfUb2ip SgREFBKJQez5G+kKO39dTL/xAJT7k9wIFlUdWo5HNZaVUAu4AmQHa86tMmwaBa2gk0eH cSWg== X-Gm-Message-State: AJIora9c0Y+1NZ9Vt2W4u35pADrY1a40bO9cxIw4Mteis2TBy8lg3xIA Mrza7pA3szUDEjMOXFabKsSVSNGWcw== X-Google-Smtp-Source: AGRyM1vnWdHTWoGNJAzy4B2waQwFaJfUSV4Y47hXN5NEtLermdhBTU15cF0iWjvrt0N4z9sorLG9Sg== X-Received: by 2002:a05:6638:1483:b0:33c:149:4e07 with SMTP id j3-20020a056638148300b0033c01494e07mr8318855jak.216.1656689345945; Fri, 01 Jul 2022 08:29:05 -0700 (PDT) Received: from robh.at.kernel.org ([64.188.179.248]) by smtp.gmail.com with ESMTPSA id h8-20020a92d848000000b002da9f82c703sm5091897ilq.5.2022.07.01.08.29.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Jul 2022 08:29:05 -0700 (PDT) Received: (nullmailer pid 981138 invoked by uid 1000); Fri, 01 Jul 2022 15:29:03 -0000 Date: Fri, 1 Jul 2022 09:29:03 -0600 From: Rob Herring To: Irui Wang Cc: Hans Verkuil , Mauro Carvalho Chehab , Matthias Brugger , Tzung-Bi Shih , angelogioacchino.delregno@collabora.com, nicolas.dufresne@collabora.com, wenst@chromium.org, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Tomasz Figa , xia.jiang@mediatek.com, maoguang.meng@mediatek.com, kyrie wu , srv_heupstream@mediatek.com Subject: Re: [V4,1/8] dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible Message-ID: <20220701152903.GA968728-robh@kernel.org> References: <20220627025540.8901-1-irui.wang@mediatek.com> <20220627025540.8901-2-irui.wang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220627025540.8901-2-irui.wang@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Jun 27, 2022 at 10:55:33AM +0800, Irui Wang wrote: > From: kyrie wu > > Add mediatek,mt8195-jpgdec compatible to binding document. > > Signed-off-by: kyrie wu > --- > .../media/mediatek,mt8195-jpegdec.yaml | 176 ++++++++++++++++++ > 1 file changed, 176 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml > new file mode 100644 > index 000000000000..8a255e8e2e09 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml > @@ -0,0 +1,176 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek JPEG Encoder Device Tree Bindings s/Device Tree Bindings// > + > +maintainers: > + - kyrie wu > + > +description: |- Don't need '|-' > + MediaTek JPEG Decoder is the JPEG decode hardware present in MediaTek SoCs > + > +properties: > + compatible: > + items: > + - const: mediatek,mt8195-jpgdec > + > + mediatek,jpegdec-multi-core: > + type: boolean > + description: | Don't need '|' > + Indicates whether the jpeg encoder has multiple cores or not. Can't this be implied from the child nodes? > + > + power-domains: > + maxItems: 1 > + > + iommus: > + maxItems: 6 > + description: | > + Points to the respective IOMMU block with master port as argument, see > + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. > + Ports are according to the HW. > + > + "#address-cells": > + const: 2 > + > + "#size-cells": > + const: 2 > + > + ranges: true > + > +# Required child node: > +patternProperties: > + "^jpgdec@[0-9a-f]+$": > + type: object > + description: | > + The jpeg decoder hardware device node which should be added as subnodes to > + the main jpeg node. > + > + properties: > + compatible: > + const: mediatek,mt8195-jpgdec-hw > + > + reg: > + maxItems: 1 > + > + hw_id: So a similar, but different property from the video codec? Either way, this property should go. We don't do indexes in DT. Why do you need this? > + description: | > + MT8195 decoding hardware id value. MT8195 has three decoding hardwares, > + which is represented by this parameter. > + > + iommus: > + minItems: 1 > + maxItems: 32 > + description: | > + List of the hardware port in respective IOMMU block for current Socs. > + Refer to bindings/iommu/mediatek,iommu.yaml. > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + items: > + - const: jpgdec > + > + power-domains: > + maxItems: 1 > + > + required: > + - compatible > + - reg > + - hw_id > + - iommus > + - interrupts > + - clocks > + - clock-names > + - power-domains > + > + additionalProperties: false > + > +required: > + - compatible > + - power-domains > + - iommus > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + jpgdec_master { > + compatible = "mediatek,mt8195-jpgdec"; > + mediatek,jpegdec-multi-core; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; > + iommus = <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA0>, > + <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA0>, > + <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA1>, > + <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>, > + <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, > + <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + jpgdec@1a040000 { > + compatible = "mediatek,mt8195-jpgdec-hw"; > + reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ > + hw_id = <0>; > + iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; > + interrupts = ; > + clocks = <&vencsys CLK_VENC_JPGDEC>; > + clock-names = "jpgdec"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; > + }; > + > + jpgdec@1a050000 { > + compatible = "mediatek,mt8195-jpgdec-hw"; > + reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ > + hw_id = <1>; > + iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; > + interrupts = ; > + clocks = <&vencsys CLK_VENC_JPGDEC_C1>; > + clock-names = "jpgdec"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; > + }; > + > + jpgdec@1b040000 { > + compatible = "mediatek,mt8195-jpgdec-hw"; > + reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ > + hw_id = <2>; > + iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, > + <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, > + <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, > + <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>, > + <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>, > + <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>; > + interrupts = ; > + clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>; > + clock-names = "jpgdec"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; > + }; > + }; > + }; > -- > 2.18.0 > >