From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBF33C43334 for ; Fri, 1 Jul 2022 18:46:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230296AbiGASqP (ORCPT ); Fri, 1 Jul 2022 14:46:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229553AbiGASqN (ORCPT ); Fri, 1 Jul 2022 14:46:13 -0400 Received: from mail-il1-f181.google.com (mail-il1-f181.google.com [209.85.166.181]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A26F731509; Fri, 1 Jul 2022 11:46:12 -0700 (PDT) Received: by mail-il1-f181.google.com with SMTP id n14so1933730ilt.10; Fri, 01 Jul 2022 11:46:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=YCxDpLwBlPepXGkzDGgiHX6IUAIxVYfbH4RlDrqpozU=; b=OpTVlCrUoCdovibCe8lhEYFaPF25bHhtLdcVAohxL0SJ+iEmjVzQxT5kF30o8R40nJ 5t65mpzFt2JY4jt8noU7v3Mj87z7piNQATEer9MvzwB3ZLb58e6fI+JVJ0U6gFcvH5qR TVKl8cJjPJsSHu7cEzugRqc+URm0POPVKZ+j4BNAF6tL6Fk+8u93uiEQDjZmcXKXNu9O 88QGtL17ia1ADUHgI/zSixsqk3twN4khyJ1Ub4yJUSCv/1BnMjzCzd/k3weAUw24WXZk TY+qmj8+ID+ZzAPPnOonxJFrETstINh+pfhoUzGqfXrsFYINl/+fOXViZ+sqrXNN9k6N oL0w== X-Gm-Message-State: AJIora/bavbw2ZBs27Moaf+bKjbhmNJyLzhtHiAzwEza6DxX0Z285SMA GpRbRKvba9vfv3lYai/XbDOzBU0olA== X-Google-Smtp-Source: AGRyM1vmCcJU7aTAizYs4y6g0psY8dvbn56iRKlXvByEcGeUeD1uRKs+viF1YrYraeb0qf42lLz73w== X-Received: by 2002:a92:d0a:0:b0:2d1:e698:5c4c with SMTP id 10-20020a920d0a000000b002d1e6985c4cmr8972116iln.316.1656701171809; Fri, 01 Jul 2022 11:46:11 -0700 (PDT) Received: from robh.at.kernel.org ([64.188.179.248]) by smtp.gmail.com with ESMTPSA id cn22-20020a0566383a1600b0033171dafaa0sm2180894jab.178.2022.07.01.11.46.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Jul 2022 11:46:11 -0700 (PDT) Received: (nullmailer pid 1301953 invoked by uid 1000); Fri, 01 Jul 2022 18:46:09 -0000 Date: Fri, 1 Jul 2022 12:46:09 -0600 From: Rob Herring To: Kartik Cc: daniel.lezcano@linaro.org, tglx@linutronix.de, krzk+dt@kernel.org, thierry.reding@gmail.com, jonathanh@nvidia.com, spujar@nvidia.com, akhilrajeev@nvidia.com, rgumasta@nvidia.com, pshete@nvidia.com, vidyas@nvidia.com, mperttunen@nvidia.com, mkumard@nvidia.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: Re: [PATCH v2 1/6] dt-bindings: timer: Add Tegra186 & Tegra234 Timer Message-ID: <20220701184609.GA1293870-robh@kernel.org> References: <1656527344-28861-1-git-send-email-kkartik@nvidia.com> <1656527344-28861-2-git-send-email-kkartik@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1656527344-28861-2-git-send-email-kkartik@nvidia.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Jun 29, 2022 at 11:58:59PM +0530, Kartik wrote: > The Tegra186 timer provides ten 29-bit timer counters and one 32-bit > timestamp counter. The Tegra234 timer provides sixteen 29-bit timer > counters and one 32-bit timestamp counter. Each NV timer selects its > timing reference signal from the 1 MHz reference generated by USEC, > TSC or either clk_m or OSC. Each TMR can be programmed to generate > one-shot, periodic, or watchdog interrupts. > > Signed-off-by: Kartik > --- > .../bindings/timer/nvidia,tegra186-timer.yaml | 111 ++++++++++++++++++ > 1 file changed, 111 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml > > diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml > new file mode 100644 > index 000000000000..5dc091532cd7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml > @@ -0,0 +1,111 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: NVIDIA Tegra186 timer > + > +maintainers: > + - Thierry Reding > + > +description: > > + The Tegra timer provides 29-bit timer counters and a 32-bit timestamp > + counter. Each NV timer selects its timing reference signal from the 1 MHz > + reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be > + programmed to generate one-shot, periodic, or watchdog interrupts. > + > + > +properties: > + compatible: > + oneOf: > + - const: nvidia,tegra186-timer > + description: > > + The Tegra186 timer provides ten 29-bit timer counters. > + - const: nvidia,tegra234-timer > + description: > > + The Tegra234 timer provides sixteen 29-bit timer counters. > + > + reg: > + maxItems: 1 > + > + interrupts: true > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: nvidia,tegra186-timer > + then: > + properties: > + interrupts: > + minItems: 1 > + maxItems: 10 > + description: > > + A list of 10 interrupts; one per each timer channels 0 through 9. The schema says it is a list of 1 to 10 interrupts. Which is it. Surely the h/w is fixed. If so, drop 'minItems' and the first sentence. > + > + - if: > + properties: > + compatible: > + contains: > + const: nvidia,tegra234-timer > + then: > + properties: > + interrupts: > + minItems: 1 > + maxItems: 16 > + description: > > + A list of 16 interrupts; one per each timer channels 0 through 15. ditto > + > +required: > + - compatible > + - reg > + - interrupts > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + timer@3010000 { > + compatible = "nvidia,tegra186-timer"; > + reg = <0x03010000 0x000e0000>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + }; > + > + - | > + #include > + #include > + > + timer@2080000 { > + compatible = "nvidia,tegra234-timer"; > + reg = <0x02080000 0x00121000>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + }; > -- > 2.17.1 > >