From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Stanimir Varbanov <svarbanov@mm-sol.com>,
Vinod Koul <vkoul@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, Johan Hovold <johan@kernel.org>,
Rob Herring <robh@kernel.org>,
Johan Hovold <johan+linaro@kernel.org>
Subject: Re: [PATCH v16 2/6] PCI: dwc: Convert msi_irq to the array
Date: Mon, 4 Jul 2022 22:09:54 +0530 [thread overview]
Message-ID: <20220704163954.GF6560@thinkpad> (raw)
In-Reply-To: <20220704152746.807550-3-dmitry.baryshkov@linaro.org>
On Mon, Jul 04, 2022 at 06:27:42PM +0300, Dmitry Baryshkov wrote:
> Qualcomm version of DWC PCIe controller supports more than 32 MSI
> interrupts, but they are routed to separate interrupts in groups of 32
> vectors. To support such configuration, change the msi_irq field into an
> array. Let the DWC core handle all interrupts that were set in this
> array.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> ---
> drivers/pci/controller/dwc/pci-dra7xx.c | 2 +-
> drivers/pci/controller/dwc/pci-exynos.c | 2 +-
> .../pci/controller/dwc/pcie-designware-host.c | 32 ++++++++++++-------
> drivers/pci/controller/dwc/pcie-designware.h | 2 +-
> drivers/pci/controller/dwc/pcie-keembay.c | 2 +-
> drivers/pci/controller/dwc/pcie-spear13xx.c | 2 +-
> drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
> 7 files changed, 26 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
> index dfcdeb432dc8..0919c96dcdbd 100644
> --- a/drivers/pci/controller/dwc/pci-dra7xx.c
> +++ b/drivers/pci/controller/dwc/pci-dra7xx.c
> @@ -483,7 +483,7 @@ static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
> return pp->irq;
>
> /* MSI IRQ is muxed */
> - pp->msi_irq = -ENODEV;
> + pp->msi_irq[0] = -ENODEV;
>
> ret = dra7xx_pcie_init_irq_domain(pp);
> if (ret < 0)
> diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c
> index 467c8d1cd7e4..4f2010bd9cd7 100644
> --- a/drivers/pci/controller/dwc/pci-exynos.c
> +++ b/drivers/pci/controller/dwc/pci-exynos.c
> @@ -292,7 +292,7 @@ static int exynos_add_pcie_port(struct exynos_pcie *ep,
> }
>
> pp->ops = &exynos_pcie_host_ops;
> - pp->msi_irq = -ENODEV;
> + pp->msi_irq[0] = -ENODEV;
>
> ret = dw_pcie_host_init(pp);
> if (ret) {
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 4418879fbf43..4c5b3f70ab17 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -257,8 +257,12 @@ int dw_pcie_allocate_domains(struct pcie_port *pp)
>
> static void dw_pcie_free_msi(struct pcie_port *pp)
> {
> - if (pp->msi_irq > 0)
> - irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL);
> + u32 ctrl;
> +
> + for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
> + if (pp->msi_irq[ctrl] > 0)
> + irq_set_chained_handler_and_data(pp->msi_irq[ctrl], NULL, NULL);
> + }
>
> irq_domain_remove(pp->msi_domain);
> irq_domain_remove(pp->irq_domain);
> @@ -369,13 +373,15 @@ int dw_pcie_host_init(struct pcie_port *pp)
> for (ctrl = 0; ctrl < num_ctrls; ctrl++)
> pp->irq_mask[ctrl] = ~0;
>
> - if (!pp->msi_irq) {
> - pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi");
> - if (pp->msi_irq < 0) {
> - pp->msi_irq = platform_get_irq(pdev, 0);
> - if (pp->msi_irq < 0)
> - return pp->msi_irq;
> + if (!pp->msi_irq[0]) {
> + int irq = platform_get_irq_byname_optional(pdev, "msi");
> +
> + if (irq < 0) {
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0)
> + return irq;
> }
> + pp->msi_irq[0] = irq;
> }
>
> pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
> @@ -384,10 +390,12 @@ int dw_pcie_host_init(struct pcie_port *pp)
> if (ret)
> return ret;
>
> - if (pp->msi_irq > 0)
> - irq_set_chained_handler_and_data(pp->msi_irq,
> - dw_chained_msi_isr,
> - pp);
> + for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
> + if (pp->msi_irq[ctrl] > 0)
> + irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
> + dw_chained_msi_isr,
> + pp);
> + }
>
> ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
> if (ret)
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index b5f528536358..acbb2598cc16 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -187,7 +187,7 @@ struct pcie_port {
> u32 io_size;
> int irq;
> const struct dw_pcie_host_ops *ops;
> - int msi_irq;
> + int msi_irq[MAX_MSI_CTRLS];
> struct irq_domain *irq_domain;
> struct irq_domain *msi_domain;
> dma_addr_t msi_data;
> diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
> index 1ac29a6eef22..297e6e926c00 100644
> --- a/drivers/pci/controller/dwc/pcie-keembay.c
> +++ b/drivers/pci/controller/dwc/pcie-keembay.c
> @@ -338,7 +338,7 @@ static int keembay_pcie_add_pcie_port(struct keembay_pcie *pcie,
> int ret;
>
> pp->ops = &keembay_pcie_host_ops;
> - pp->msi_irq = -ENODEV;
> + pp->msi_irq[0] = -ENODEV;
>
> ret = keembay_pcie_setup_msi_irq(pcie);
> if (ret)
> diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/controller/dwc/pcie-spear13xx.c
> index 1569e82b5568..cc7776833810 100644
> --- a/drivers/pci/controller/dwc/pcie-spear13xx.c
> +++ b/drivers/pci/controller/dwc/pcie-spear13xx.c
> @@ -172,7 +172,7 @@ static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
> }
>
> pp->ops = &spear13xx_pcie_host_ops;
> - pp->msi_irq = -ENODEV;
> + pp->msi_irq[0] = -ENODEV;
>
> ret = dw_pcie_host_init(pp);
> if (ret) {
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index d992371a36e6..35427b7b0b5e 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -2263,7 +2263,7 @@ static void tegra194_pcie_shutdown(struct platform_device *pdev)
>
> disable_irq(pcie->pci.pp.irq);
> if (IS_ENABLED(CONFIG_PCI_MSI))
> - disable_irq(pcie->pci.pp.msi_irq);
> + disable_irq(pcie->pci.pp.msi_irq[0]);
>
> tegra194_pcie_pme_turnoff(pcie);
> tegra_pcie_unconfig_controller(pcie);
> --
> 2.35.1
>
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2022-07-04 16:42 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-04 15:27 [PATCH v16 0/6] PCI: dwc: Fix higher MSI vectors handling Dmitry Baryshkov
2022-07-04 15:27 ` [PATCH v16 1/6] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() Dmitry Baryshkov
2022-07-04 16:38 ` Manivannan Sadhasivam
2022-07-04 15:27 ` [PATCH v16 2/6] PCI: dwc: Convert msi_irq to the array Dmitry Baryshkov
2022-07-04 16:39 ` Manivannan Sadhasivam [this message]
2022-07-04 15:27 ` [PATCH v16 3/6] PCI: dwc: split MSI IRQ parsing/allocation to a separate function Dmitry Baryshkov
2022-07-04 16:41 ` Manivannan Sadhasivam
2022-07-04 15:27 ` [PATCH v16 4/6] PCI: dwc: Handle MSIs routed to multiple GIC interrupts Dmitry Baryshkov
2022-07-04 16:44 ` Manivannan Sadhasivam
2022-07-04 15:27 ` [PATCH v16 5/6] dt-bindings: PCI: qcom: Support additional MSI interrupts Dmitry Baryshkov
2022-07-07 8:06 ` Johan Hovold
2022-07-07 13:48 ` Dmitry Baryshkov
2022-07-04 15:27 ` [PATCH v16 6/6] arm64: dts: qcom: sm8250: provide " Dmitry Baryshkov
2022-07-04 16:46 ` Manivannan Sadhasivam
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