* [PATCH v16 1/6] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi()
2022-07-04 15:27 [PATCH v16 0/6] PCI: dwc: Fix higher MSI vectors handling Dmitry Baryshkov
@ 2022-07-04 15:27 ` Dmitry Baryshkov
2022-07-04 16:38 ` Manivannan Sadhasivam
2022-07-04 15:27 ` [PATCH v16 2/6] PCI: dwc: Convert msi_irq to the array Dmitry Baryshkov
` (4 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Dmitry Baryshkov @ 2022-07-04 15:27 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Manivannan Sadhasivam
Cc: Vinod Koul, linux-arm-msm, linux-pci, devicetree, Johan Hovold,
Rob Herring, Johan Hovold
The subdrivers pass -ESOMETHING if they do not want the core to touch
MSI IRQ. dw_pcie_host_init() also checks if (msi_irq > 0) rather than
just if (msi_irq). So let's make dw_pcie_free_msi() also check that
msi_irq is greater than zero.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/pci/controller/dwc/pcie-designware-host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 1e3972c487b5..4418879fbf43 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -257,7 +257,7 @@ int dw_pcie_allocate_domains(struct pcie_port *pp)
static void dw_pcie_free_msi(struct pcie_port *pp)
{
- if (pp->msi_irq)
+ if (pp->msi_irq > 0)
irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL);
irq_domain_remove(pp->msi_domain);
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v16 1/6] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi()
2022-07-04 15:27 ` [PATCH v16 1/6] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() Dmitry Baryshkov
@ 2022-07-04 16:38 ` Manivannan Sadhasivam
0 siblings, 0 replies; 14+ messages in thread
From: Manivannan Sadhasivam @ 2022-07-04 16:38 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Vinod Koul, linux-arm-msm, linux-pci,
devicetree, Johan Hovold, Rob Herring, Johan Hovold
On Mon, Jul 04, 2022 at 06:27:41PM +0300, Dmitry Baryshkov wrote:
> The subdrivers pass -ESOMETHING if they do not want the core to touch
> MSI IRQ. dw_pcie_host_init() also checks if (msi_irq > 0) rather than
> just if (msi_irq). So let's make dw_pcie_free_msi() also check that
> msi_irq is greater than zero.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> ---
> drivers/pci/controller/dwc/pcie-designware-host.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 1e3972c487b5..4418879fbf43 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -257,7 +257,7 @@ int dw_pcie_allocate_domains(struct pcie_port *pp)
>
> static void dw_pcie_free_msi(struct pcie_port *pp)
> {
> - if (pp->msi_irq)
> + if (pp->msi_irq > 0)
> irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL);
>
> irq_domain_remove(pp->msi_domain);
> --
> 2.35.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v16 2/6] PCI: dwc: Convert msi_irq to the array
2022-07-04 15:27 [PATCH v16 0/6] PCI: dwc: Fix higher MSI vectors handling Dmitry Baryshkov
2022-07-04 15:27 ` [PATCH v16 1/6] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() Dmitry Baryshkov
@ 2022-07-04 15:27 ` Dmitry Baryshkov
2022-07-04 16:39 ` Manivannan Sadhasivam
2022-07-04 15:27 ` [PATCH v16 3/6] PCI: dwc: split MSI IRQ parsing/allocation to a separate function Dmitry Baryshkov
` (3 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Dmitry Baryshkov @ 2022-07-04 15:27 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Manivannan Sadhasivam
Cc: Vinod Koul, linux-arm-msm, linux-pci, devicetree, Johan Hovold,
Rob Herring, Johan Hovold
Qualcomm version of DWC PCIe controller supports more than 32 MSI
interrupts, but they are routed to separate interrupts in groups of 32
vectors. To support such configuration, change the msi_irq field into an
array. Let the DWC core handle all interrupts that were set in this
array.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/pci/controller/dwc/pci-dra7xx.c | 2 +-
drivers/pci/controller/dwc/pci-exynos.c | 2 +-
.../pci/controller/dwc/pcie-designware-host.c | 32 ++++++++++++-------
drivers/pci/controller/dwc/pcie-designware.h | 2 +-
drivers/pci/controller/dwc/pcie-keembay.c | 2 +-
drivers/pci/controller/dwc/pcie-spear13xx.c | 2 +-
drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
7 files changed, 26 insertions(+), 18 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
index dfcdeb432dc8..0919c96dcdbd 100644
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -483,7 +483,7 @@ static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
return pp->irq;
/* MSI IRQ is muxed */
- pp->msi_irq = -ENODEV;
+ pp->msi_irq[0] = -ENODEV;
ret = dra7xx_pcie_init_irq_domain(pp);
if (ret < 0)
diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c
index 467c8d1cd7e4..4f2010bd9cd7 100644
--- a/drivers/pci/controller/dwc/pci-exynos.c
+++ b/drivers/pci/controller/dwc/pci-exynos.c
@@ -292,7 +292,7 @@ static int exynos_add_pcie_port(struct exynos_pcie *ep,
}
pp->ops = &exynos_pcie_host_ops;
- pp->msi_irq = -ENODEV;
+ pp->msi_irq[0] = -ENODEV;
ret = dw_pcie_host_init(pp);
if (ret) {
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 4418879fbf43..4c5b3f70ab17 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -257,8 +257,12 @@ int dw_pcie_allocate_domains(struct pcie_port *pp)
static void dw_pcie_free_msi(struct pcie_port *pp)
{
- if (pp->msi_irq > 0)
- irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL);
+ u32 ctrl;
+
+ for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
+ if (pp->msi_irq[ctrl] > 0)
+ irq_set_chained_handler_and_data(pp->msi_irq[ctrl], NULL, NULL);
+ }
irq_domain_remove(pp->msi_domain);
irq_domain_remove(pp->irq_domain);
@@ -369,13 +373,15 @@ int dw_pcie_host_init(struct pcie_port *pp)
for (ctrl = 0; ctrl < num_ctrls; ctrl++)
pp->irq_mask[ctrl] = ~0;
- if (!pp->msi_irq) {
- pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi");
- if (pp->msi_irq < 0) {
- pp->msi_irq = platform_get_irq(pdev, 0);
- if (pp->msi_irq < 0)
- return pp->msi_irq;
+ if (!pp->msi_irq[0]) {
+ int irq = platform_get_irq_byname_optional(pdev, "msi");
+
+ if (irq < 0) {
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
}
+ pp->msi_irq[0] = irq;
}
pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
@@ -384,10 +390,12 @@ int dw_pcie_host_init(struct pcie_port *pp)
if (ret)
return ret;
- if (pp->msi_irq > 0)
- irq_set_chained_handler_and_data(pp->msi_irq,
- dw_chained_msi_isr,
- pp);
+ for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
+ if (pp->msi_irq[ctrl] > 0)
+ irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
+ dw_chained_msi_isr,
+ pp);
+ }
ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
if (ret)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index b5f528536358..acbb2598cc16 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -187,7 +187,7 @@ struct pcie_port {
u32 io_size;
int irq;
const struct dw_pcie_host_ops *ops;
- int msi_irq;
+ int msi_irq[MAX_MSI_CTRLS];
struct irq_domain *irq_domain;
struct irq_domain *msi_domain;
dma_addr_t msi_data;
diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
index 1ac29a6eef22..297e6e926c00 100644
--- a/drivers/pci/controller/dwc/pcie-keembay.c
+++ b/drivers/pci/controller/dwc/pcie-keembay.c
@@ -338,7 +338,7 @@ static int keembay_pcie_add_pcie_port(struct keembay_pcie *pcie,
int ret;
pp->ops = &keembay_pcie_host_ops;
- pp->msi_irq = -ENODEV;
+ pp->msi_irq[0] = -ENODEV;
ret = keembay_pcie_setup_msi_irq(pcie);
if (ret)
diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/controller/dwc/pcie-spear13xx.c
index 1569e82b5568..cc7776833810 100644
--- a/drivers/pci/controller/dwc/pcie-spear13xx.c
+++ b/drivers/pci/controller/dwc/pcie-spear13xx.c
@@ -172,7 +172,7 @@ static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
}
pp->ops = &spear13xx_pcie_host_ops;
- pp->msi_irq = -ENODEV;
+ pp->msi_irq[0] = -ENODEV;
ret = dw_pcie_host_init(pp);
if (ret) {
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index d992371a36e6..35427b7b0b5e 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -2263,7 +2263,7 @@ static void tegra194_pcie_shutdown(struct platform_device *pdev)
disable_irq(pcie->pci.pp.irq);
if (IS_ENABLED(CONFIG_PCI_MSI))
- disable_irq(pcie->pci.pp.msi_irq);
+ disable_irq(pcie->pci.pp.msi_irq[0]);
tegra194_pcie_pme_turnoff(pcie);
tegra_pcie_unconfig_controller(pcie);
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v16 2/6] PCI: dwc: Convert msi_irq to the array
2022-07-04 15:27 ` [PATCH v16 2/6] PCI: dwc: Convert msi_irq to the array Dmitry Baryshkov
@ 2022-07-04 16:39 ` Manivannan Sadhasivam
0 siblings, 0 replies; 14+ messages in thread
From: Manivannan Sadhasivam @ 2022-07-04 16:39 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Vinod Koul, linux-arm-msm, linux-pci,
devicetree, Johan Hovold, Rob Herring, Johan Hovold
On Mon, Jul 04, 2022 at 06:27:42PM +0300, Dmitry Baryshkov wrote:
> Qualcomm version of DWC PCIe controller supports more than 32 MSI
> interrupts, but they are routed to separate interrupts in groups of 32
> vectors. To support such configuration, change the msi_irq field into an
> array. Let the DWC core handle all interrupts that were set in this
> array.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> ---
> drivers/pci/controller/dwc/pci-dra7xx.c | 2 +-
> drivers/pci/controller/dwc/pci-exynos.c | 2 +-
> .../pci/controller/dwc/pcie-designware-host.c | 32 ++++++++++++-------
> drivers/pci/controller/dwc/pcie-designware.h | 2 +-
> drivers/pci/controller/dwc/pcie-keembay.c | 2 +-
> drivers/pci/controller/dwc/pcie-spear13xx.c | 2 +-
> drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
> 7 files changed, 26 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
> index dfcdeb432dc8..0919c96dcdbd 100644
> --- a/drivers/pci/controller/dwc/pci-dra7xx.c
> +++ b/drivers/pci/controller/dwc/pci-dra7xx.c
> @@ -483,7 +483,7 @@ static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
> return pp->irq;
>
> /* MSI IRQ is muxed */
> - pp->msi_irq = -ENODEV;
> + pp->msi_irq[0] = -ENODEV;
>
> ret = dra7xx_pcie_init_irq_domain(pp);
> if (ret < 0)
> diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c
> index 467c8d1cd7e4..4f2010bd9cd7 100644
> --- a/drivers/pci/controller/dwc/pci-exynos.c
> +++ b/drivers/pci/controller/dwc/pci-exynos.c
> @@ -292,7 +292,7 @@ static int exynos_add_pcie_port(struct exynos_pcie *ep,
> }
>
> pp->ops = &exynos_pcie_host_ops;
> - pp->msi_irq = -ENODEV;
> + pp->msi_irq[0] = -ENODEV;
>
> ret = dw_pcie_host_init(pp);
> if (ret) {
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 4418879fbf43..4c5b3f70ab17 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -257,8 +257,12 @@ int dw_pcie_allocate_domains(struct pcie_port *pp)
>
> static void dw_pcie_free_msi(struct pcie_port *pp)
> {
> - if (pp->msi_irq > 0)
> - irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL);
> + u32 ctrl;
> +
> + for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
> + if (pp->msi_irq[ctrl] > 0)
> + irq_set_chained_handler_and_data(pp->msi_irq[ctrl], NULL, NULL);
> + }
>
> irq_domain_remove(pp->msi_domain);
> irq_domain_remove(pp->irq_domain);
> @@ -369,13 +373,15 @@ int dw_pcie_host_init(struct pcie_port *pp)
> for (ctrl = 0; ctrl < num_ctrls; ctrl++)
> pp->irq_mask[ctrl] = ~0;
>
> - if (!pp->msi_irq) {
> - pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi");
> - if (pp->msi_irq < 0) {
> - pp->msi_irq = platform_get_irq(pdev, 0);
> - if (pp->msi_irq < 0)
> - return pp->msi_irq;
> + if (!pp->msi_irq[0]) {
> + int irq = platform_get_irq_byname_optional(pdev, "msi");
> +
> + if (irq < 0) {
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0)
> + return irq;
> }
> + pp->msi_irq[0] = irq;
> }
>
> pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
> @@ -384,10 +390,12 @@ int dw_pcie_host_init(struct pcie_port *pp)
> if (ret)
> return ret;
>
> - if (pp->msi_irq > 0)
> - irq_set_chained_handler_and_data(pp->msi_irq,
> - dw_chained_msi_isr,
> - pp);
> + for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
> + if (pp->msi_irq[ctrl] > 0)
> + irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
> + dw_chained_msi_isr,
> + pp);
> + }
>
> ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
> if (ret)
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index b5f528536358..acbb2598cc16 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -187,7 +187,7 @@ struct pcie_port {
> u32 io_size;
> int irq;
> const struct dw_pcie_host_ops *ops;
> - int msi_irq;
> + int msi_irq[MAX_MSI_CTRLS];
> struct irq_domain *irq_domain;
> struct irq_domain *msi_domain;
> dma_addr_t msi_data;
> diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
> index 1ac29a6eef22..297e6e926c00 100644
> --- a/drivers/pci/controller/dwc/pcie-keembay.c
> +++ b/drivers/pci/controller/dwc/pcie-keembay.c
> @@ -338,7 +338,7 @@ static int keembay_pcie_add_pcie_port(struct keembay_pcie *pcie,
> int ret;
>
> pp->ops = &keembay_pcie_host_ops;
> - pp->msi_irq = -ENODEV;
> + pp->msi_irq[0] = -ENODEV;
>
> ret = keembay_pcie_setup_msi_irq(pcie);
> if (ret)
> diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/controller/dwc/pcie-spear13xx.c
> index 1569e82b5568..cc7776833810 100644
> --- a/drivers/pci/controller/dwc/pcie-spear13xx.c
> +++ b/drivers/pci/controller/dwc/pcie-spear13xx.c
> @@ -172,7 +172,7 @@ static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
> }
>
> pp->ops = &spear13xx_pcie_host_ops;
> - pp->msi_irq = -ENODEV;
> + pp->msi_irq[0] = -ENODEV;
>
> ret = dw_pcie_host_init(pp);
> if (ret) {
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index d992371a36e6..35427b7b0b5e 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -2263,7 +2263,7 @@ static void tegra194_pcie_shutdown(struct platform_device *pdev)
>
> disable_irq(pcie->pci.pp.irq);
> if (IS_ENABLED(CONFIG_PCI_MSI))
> - disable_irq(pcie->pci.pp.msi_irq);
> + disable_irq(pcie->pci.pp.msi_irq[0]);
>
> tegra194_pcie_pme_turnoff(pcie);
> tegra_pcie_unconfig_controller(pcie);
> --
> 2.35.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v16 3/6] PCI: dwc: split MSI IRQ parsing/allocation to a separate function
2022-07-04 15:27 [PATCH v16 0/6] PCI: dwc: Fix higher MSI vectors handling Dmitry Baryshkov
2022-07-04 15:27 ` [PATCH v16 1/6] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() Dmitry Baryshkov
2022-07-04 15:27 ` [PATCH v16 2/6] PCI: dwc: Convert msi_irq to the array Dmitry Baryshkov
@ 2022-07-04 15:27 ` Dmitry Baryshkov
2022-07-04 16:41 ` Manivannan Sadhasivam
2022-07-04 15:27 ` [PATCH v16 4/6] PCI: dwc: Handle MSIs routed to multiple GIC interrupts Dmitry Baryshkov
` (2 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Dmitry Baryshkov @ 2022-07-04 15:27 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Manivannan Sadhasivam
Cc: Vinod Koul, linux-arm-msm, linux-pci, devicetree, Johan Hovold,
Rob Herring, Johan Hovold
Split handling of MSI host IRQs to a separate dw_pcie_msi_host_init()
function. The code is complex enough to warrant a separate function.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../pci/controller/dwc/pcie-designware-host.c | 101 ++++++++++--------
1 file changed, 57 insertions(+), 44 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 4c5b3f70ab17..3ba531da99d4 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -290,6 +290,61 @@ static void dw_pcie_msi_init(struct pcie_port *pp)
dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
}
+static int dw_pcie_msi_host_init(struct pcie_port *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct device *dev = pci->dev;
+ struct platform_device *pdev = to_platform_device(dev);
+ int ret;
+ u32 ctrl, num_ctrls;
+
+ num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
+ for (ctrl = 0; ctrl < num_ctrls; ctrl++)
+ pp->irq_mask[ctrl] = ~0;
+
+ if (!pp->msi_irq[0]) {
+ int irq = platform_get_irq_byname_optional(pdev, "msi");
+
+ if (irq < 0) {
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+ }
+ pp->msi_irq[0] = irq;
+ }
+
+ pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
+
+ ret = dw_pcie_allocate_domains(pp);
+ if (ret)
+ return ret;
+
+ for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
+ if (pp->msi_irq[ctrl] > 0)
+ irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
+ dw_chained_msi_isr,
+ pp);
+ }
+
+ ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
+ if (ret)
+ dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
+
+ pp->msi_page = alloc_page(GFP_DMA32);
+ pp->msi_data = dma_map_page(pci->dev, pp->msi_page, 0,
+ PAGE_SIZE, DMA_FROM_DEVICE);
+ ret = dma_mapping_error(pci->dev, pp->msi_data);
+ if (ret) {
+ dev_err(pci->dev, "Failed to map MSI data\n");
+ pp->msi_page = NULL;
+ pp->msi_data = 0;
+ dw_pcie_free_msi(pp);
+ return ret;
+ }
+
+ return 0;
+}
+
int dw_pcie_host_init(struct pcie_port *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
@@ -367,51 +422,9 @@ int dw_pcie_host_init(struct pcie_port *pp)
if (ret < 0)
return ret;
} else if (pp->has_msi_ctrl) {
- u32 ctrl, num_ctrls;
-
- num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
- for (ctrl = 0; ctrl < num_ctrls; ctrl++)
- pp->irq_mask[ctrl] = ~0;
-
- if (!pp->msi_irq[0]) {
- int irq = platform_get_irq_byname_optional(pdev, "msi");
-
- if (irq < 0) {
- irq = platform_get_irq(pdev, 0);
- if (irq < 0)
- return irq;
- }
- pp->msi_irq[0] = irq;
- }
-
- pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
-
- ret = dw_pcie_allocate_domains(pp);
- if (ret)
+ ret = dw_pcie_msi_host_init(pp);
+ if (ret < 0)
return ret;
-
- for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
- if (pp->msi_irq[ctrl] > 0)
- irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
- dw_chained_msi_isr,
- pp);
- }
-
- ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
- if (ret)
- dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
-
- pp->msi_page = alloc_page(GFP_DMA32);
- pp->msi_data = dma_map_page(pci->dev, pp->msi_page, 0,
- PAGE_SIZE, DMA_FROM_DEVICE);
- ret = dma_mapping_error(pci->dev, pp->msi_data);
- if (ret) {
- dev_err(pci->dev, "Failed to map MSI data\n");
- __free_page(pp->msi_page);
- pp->msi_page = NULL;
- pp->msi_data = 0;
- goto err_free_msi;
- }
}
}
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v16 3/6] PCI: dwc: split MSI IRQ parsing/allocation to a separate function
2022-07-04 15:27 ` [PATCH v16 3/6] PCI: dwc: split MSI IRQ parsing/allocation to a separate function Dmitry Baryshkov
@ 2022-07-04 16:41 ` Manivannan Sadhasivam
0 siblings, 0 replies; 14+ messages in thread
From: Manivannan Sadhasivam @ 2022-07-04 16:41 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Vinod Koul, linux-arm-msm, linux-pci,
devicetree, Johan Hovold, Rob Herring, Johan Hovold
On Mon, Jul 04, 2022 at 06:27:43PM +0300, Dmitry Baryshkov wrote:
> Split handling of MSI host IRQs to a separate dw_pcie_msi_host_init()
> function. The code is complex enough to warrant a separate function.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> ---
> .../pci/controller/dwc/pcie-designware-host.c | 101 ++++++++++--------
> 1 file changed, 57 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 4c5b3f70ab17..3ba531da99d4 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -290,6 +290,61 @@ static void dw_pcie_msi_init(struct pcie_port *pp)
> dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
> }
>
> +static int dw_pcie_msi_host_init(struct pcie_port *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct device *dev = pci->dev;
> + struct platform_device *pdev = to_platform_device(dev);
> + int ret;
> + u32 ctrl, num_ctrls;
> +
> + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
> + for (ctrl = 0; ctrl < num_ctrls; ctrl++)
> + pp->irq_mask[ctrl] = ~0;
> +
> + if (!pp->msi_irq[0]) {
> + int irq = platform_get_irq_byname_optional(pdev, "msi");
> +
> + if (irq < 0) {
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0)
> + return irq;
> + }
> + pp->msi_irq[0] = irq;
> + }
> +
> + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
> +
> + ret = dw_pcie_allocate_domains(pp);
> + if (ret)
> + return ret;
> +
> + for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
> + if (pp->msi_irq[ctrl] > 0)
> + irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
> + dw_chained_msi_isr,
> + pp);
> + }
> +
> + ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
> + if (ret)
> + dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
> +
> + pp->msi_page = alloc_page(GFP_DMA32);
> + pp->msi_data = dma_map_page(pci->dev, pp->msi_page, 0,
> + PAGE_SIZE, DMA_FROM_DEVICE);
> + ret = dma_mapping_error(pci->dev, pp->msi_data);
> + if (ret) {
> + dev_err(pci->dev, "Failed to map MSI data\n");
> + pp->msi_page = NULL;
> + pp->msi_data = 0;
> + dw_pcie_free_msi(pp);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> int dw_pcie_host_init(struct pcie_port *pp)
> {
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> @@ -367,51 +422,9 @@ int dw_pcie_host_init(struct pcie_port *pp)
> if (ret < 0)
> return ret;
> } else if (pp->has_msi_ctrl) {
> - u32 ctrl, num_ctrls;
> -
> - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
> - for (ctrl = 0; ctrl < num_ctrls; ctrl++)
> - pp->irq_mask[ctrl] = ~0;
> -
> - if (!pp->msi_irq[0]) {
> - int irq = platform_get_irq_byname_optional(pdev, "msi");
> -
> - if (irq < 0) {
> - irq = platform_get_irq(pdev, 0);
> - if (irq < 0)
> - return irq;
> - }
> - pp->msi_irq[0] = irq;
> - }
> -
> - pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
> -
> - ret = dw_pcie_allocate_domains(pp);
> - if (ret)
> + ret = dw_pcie_msi_host_init(pp);
> + if (ret < 0)
> return ret;
> -
> - for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
> - if (pp->msi_irq[ctrl] > 0)
> - irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
> - dw_chained_msi_isr,
> - pp);
> - }
> -
> - ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
> - if (ret)
> - dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
> -
> - pp->msi_page = alloc_page(GFP_DMA32);
> - pp->msi_data = dma_map_page(pci->dev, pp->msi_page, 0,
> - PAGE_SIZE, DMA_FROM_DEVICE);
> - ret = dma_mapping_error(pci->dev, pp->msi_data);
> - if (ret) {
> - dev_err(pci->dev, "Failed to map MSI data\n");
> - __free_page(pp->msi_page);
> - pp->msi_page = NULL;
> - pp->msi_data = 0;
> - goto err_free_msi;
> - }
> }
> }
>
> --
> 2.35.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v16 4/6] PCI: dwc: Handle MSIs routed to multiple GIC interrupts
2022-07-04 15:27 [PATCH v16 0/6] PCI: dwc: Fix higher MSI vectors handling Dmitry Baryshkov
` (2 preceding siblings ...)
2022-07-04 15:27 ` [PATCH v16 3/6] PCI: dwc: split MSI IRQ parsing/allocation to a separate function Dmitry Baryshkov
@ 2022-07-04 15:27 ` Dmitry Baryshkov
2022-07-04 16:44 ` Manivannan Sadhasivam
2022-07-04 15:27 ` [PATCH v16 5/6] dt-bindings: PCI: qcom: Support additional MSI interrupts Dmitry Baryshkov
2022-07-04 15:27 ` [PATCH v16 6/6] arm64: dts: qcom: sm8250: provide " Dmitry Baryshkov
5 siblings, 1 reply; 14+ messages in thread
From: Dmitry Baryshkov @ 2022-07-04 15:27 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Manivannan Sadhasivam
Cc: Vinod Koul, linux-arm-msm, linux-pci, devicetree, Johan Hovold,
Rob Herring, Johan Hovold
On some of Qualcomm platforms each group of 32 MSI vectors is routed to the
separate GIC interrupt. Implement support for such configurations by
parsing "msi0" ... "msiN" interrupts and attaching them to the chained
handler.
Note, that if DT doesn't list an array of MSI interrupts and uses single
"msi" IRQ, the driver will limit the amount of supported MSI vectors
accordingly (to 32).
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../pci/controller/dwc/pcie-designware-host.c | 63 +++++++++++++++++--
1 file changed, 59 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 3ba531da99d4..2bab0c395ea9 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -290,6 +290,46 @@ static void dw_pcie_msi_init(struct pcie_port *pp)
dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
}
+static int dw_pcie_parse_split_msi_irq(struct pcie_port *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct device *dev = pci->dev;
+ struct platform_device *pdev = to_platform_device(dev);
+ int irq;
+ u32 ctrl, max_vectors;
+
+ /* Parse as many IRQs as described in the devicetree. */
+ for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
+ char msi_name[] = "msiX";
+
+ msi_name[3] = '0' + ctrl;
+ irq = platform_get_irq_byname_optional(pdev, msi_name);
+ if (irq == -ENXIO)
+ break;
+ if (irq < 0)
+ return dev_err_probe(dev, irq,
+ "Failed to parse MSI IRQ '%s'\n",
+ msi_name);
+
+ pp->msi_irq[ctrl] = irq;
+ }
+
+ /* If there were no "msiN" IRQs at all, fallback to the standard "msi" IRQ. */
+ if (ctrl == 0)
+ return -ENXIO;
+
+ max_vectors = ctrl * MAX_MSI_IRQS_PER_CTRL;
+ if (pp->num_vectors > max_vectors) {
+ dev_warn(dev, "Exceeding number of MSI vectors, limiting to %u\n",
+ max_vectors);
+ pp->num_vectors = max_vectors;
+ }
+ if (!pp->num_vectors)
+ pp->num_vectors = max_vectors;
+
+ return 0;
+}
+
static int dw_pcie_msi_host_init(struct pcie_port *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
@@ -298,21 +338,32 @@ static int dw_pcie_msi_host_init(struct pcie_port *pp)
int ret;
u32 ctrl, num_ctrls;
- num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
- for (ctrl = 0; ctrl < num_ctrls; ctrl++)
+ for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++)
pp->irq_mask[ctrl] = ~0;
+ if (!pp->msi_irq[0]) {
+ ret = dw_pcie_parse_split_msi_irq(pp);
+ if (ret < 0 && ret != -ENXIO)
+ return ret;
+ }
+
+ if (!pp->num_vectors)
+ pp->num_vectors = MSI_DEF_NUM_VECTORS;
+ num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
+
if (!pp->msi_irq[0]) {
int irq = platform_get_irq_byname_optional(pdev, "msi");
if (irq < 0) {
irq = platform_get_irq(pdev, 0);
if (irq < 0)
- return irq;
+ return dev_err_probe(dev, irq, "Failed to parse MSI irq\n");
}
pp->msi_irq[0] = irq;
}
+ dev_dbg(dev, "Using %d MSI vectors\n", pp->num_vectors);
+
pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
ret = dw_pcie_allocate_domains(pp);
@@ -410,7 +461,11 @@ int dw_pcie_host_init(struct pcie_port *pp)
of_property_read_bool(np, "msi-parent") ||
of_property_read_bool(np, "msi-map"));
- if (!pp->num_vectors) {
+ /*
+ * For the has_msi_ctrl case the default assignment is handled
+ * in the dw_pcie_msi_host_init().
+ */
+ if (!pp->has_msi_ctrl && !pp->num_vectors) {
pp->num_vectors = MSI_DEF_NUM_VECTORS;
} else if (pp->num_vectors > MAX_MSI_IRQS) {
dev_err(dev, "Invalid number of vectors\n");
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v16 4/6] PCI: dwc: Handle MSIs routed to multiple GIC interrupts
2022-07-04 15:27 ` [PATCH v16 4/6] PCI: dwc: Handle MSIs routed to multiple GIC interrupts Dmitry Baryshkov
@ 2022-07-04 16:44 ` Manivannan Sadhasivam
0 siblings, 0 replies; 14+ messages in thread
From: Manivannan Sadhasivam @ 2022-07-04 16:44 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Vinod Koul, linux-arm-msm, linux-pci,
devicetree, Johan Hovold, Rob Herring, Johan Hovold
On Mon, Jul 04, 2022 at 06:27:44PM +0300, Dmitry Baryshkov wrote:
> On some of Qualcomm platforms each group of 32 MSI vectors is routed to the
> separate GIC interrupt. Implement support for such configurations by
> parsing "msi0" ... "msiN" interrupts and attaching them to the chained
> handler.
>
> Note, that if DT doesn't list an array of MSI interrupts and uses single
> "msi" IRQ, the driver will limit the amount of supported MSI vectors
> accordingly (to 32).
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> ---
> .../pci/controller/dwc/pcie-designware-host.c | 63 +++++++++++++++++--
> 1 file changed, 59 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 3ba531da99d4..2bab0c395ea9 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -290,6 +290,46 @@ static void dw_pcie_msi_init(struct pcie_port *pp)
> dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
> }
>
> +static int dw_pcie_parse_split_msi_irq(struct pcie_port *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct device *dev = pci->dev;
> + struct platform_device *pdev = to_platform_device(dev);
> + int irq;
> + u32 ctrl, max_vectors;
> +
> + /* Parse as many IRQs as described in the devicetree. */
> + for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
> + char msi_name[] = "msiX";
> +
> + msi_name[3] = '0' + ctrl;
> + irq = platform_get_irq_byname_optional(pdev, msi_name);
> + if (irq == -ENXIO)
> + break;
> + if (irq < 0)
> + return dev_err_probe(dev, irq,
> + "Failed to parse MSI IRQ '%s'\n",
> + msi_name);
> +
> + pp->msi_irq[ctrl] = irq;
> + }
> +
> + /* If there were no "msiN" IRQs at all, fallback to the standard "msi" IRQ. */
> + if (ctrl == 0)
> + return -ENXIO;
> +
> + max_vectors = ctrl * MAX_MSI_IRQS_PER_CTRL;
> + if (pp->num_vectors > max_vectors) {
> + dev_warn(dev, "Exceeding number of MSI vectors, limiting to %u\n",
> + max_vectors);
> + pp->num_vectors = max_vectors;
> + }
> + if (!pp->num_vectors)
> + pp->num_vectors = max_vectors;
> +
> + return 0;
> +}
> +
> static int dw_pcie_msi_host_init(struct pcie_port *pp)
> {
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> @@ -298,21 +338,32 @@ static int dw_pcie_msi_host_init(struct pcie_port *pp)
> int ret;
> u32 ctrl, num_ctrls;
>
> - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
> - for (ctrl = 0; ctrl < num_ctrls; ctrl++)
> + for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++)
> pp->irq_mask[ctrl] = ~0;
>
> + if (!pp->msi_irq[0]) {
> + ret = dw_pcie_parse_split_msi_irq(pp);
> + if (ret < 0 && ret != -ENXIO)
> + return ret;
> + }
> +
> + if (!pp->num_vectors)
> + pp->num_vectors = MSI_DEF_NUM_VECTORS;
> + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
> +
> if (!pp->msi_irq[0]) {
> int irq = platform_get_irq_byname_optional(pdev, "msi");
>
> if (irq < 0) {
> irq = platform_get_irq(pdev, 0);
> if (irq < 0)
> - return irq;
> + return dev_err_probe(dev, irq, "Failed to parse MSI irq\n");
> }
> pp->msi_irq[0] = irq;
> }
>
> + dev_dbg(dev, "Using %d MSI vectors\n", pp->num_vectors);
> +
> pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
>
> ret = dw_pcie_allocate_domains(pp);
> @@ -410,7 +461,11 @@ int dw_pcie_host_init(struct pcie_port *pp)
> of_property_read_bool(np, "msi-parent") ||
> of_property_read_bool(np, "msi-map"));
>
> - if (!pp->num_vectors) {
> + /*
> + * For the has_msi_ctrl case the default assignment is handled
> + * in the dw_pcie_msi_host_init().
> + */
> + if (!pp->has_msi_ctrl && !pp->num_vectors) {
> pp->num_vectors = MSI_DEF_NUM_VECTORS;
> } else if (pp->num_vectors > MAX_MSI_IRQS) {
> dev_err(dev, "Invalid number of vectors\n");
> --
> 2.35.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v16 5/6] dt-bindings: PCI: qcom: Support additional MSI interrupts
2022-07-04 15:27 [PATCH v16 0/6] PCI: dwc: Fix higher MSI vectors handling Dmitry Baryshkov
` (3 preceding siblings ...)
2022-07-04 15:27 ` [PATCH v16 4/6] PCI: dwc: Handle MSIs routed to multiple GIC interrupts Dmitry Baryshkov
@ 2022-07-04 15:27 ` Dmitry Baryshkov
2022-07-07 8:06 ` Johan Hovold
2022-07-04 15:27 ` [PATCH v16 6/6] arm64: dts: qcom: sm8250: provide " Dmitry Baryshkov
5 siblings, 1 reply; 14+ messages in thread
From: Dmitry Baryshkov @ 2022-07-04 15:27 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Manivannan Sadhasivam
Cc: Vinod Koul, linux-arm-msm, linux-pci, devicetree, Johan Hovold,
Krzysztof Kozlowski, Rob Herring
On Qualcomm platforms each group of 32 MSI vectors is routed to the
separate GIC interrupt. Document mapping of additional interrupts.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/pci/qcom,pcie.yaml | 51 +++++++++++++++++--
1 file changed, 48 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index c40ba753707c..ee5414522e3c 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -43,11 +43,12 @@ properties:
maxItems: 5
interrupts:
- maxItems: 1
+ minItems: 1
+ maxItems: 8
interrupt-names:
- items:
- - const: msi
+ minItems: 1
+ maxItems: 8
# Common definitions for clocks, clock-names and reset.
# Platform constraints are described later.
@@ -623,6 +624,50 @@ allOf:
- resets
- reset-names
+ # On newer chipsets support either 1 or 8 msi interrupts
+ # On older chipsets it's always 1 msi interrupt
+ - if:
+ properties:
+ compatibles:
+ contains:
+ enum:
+ - qcom,pcie-msm8996
+ - qcom,pcie-sc7280
+ - qcom,pcie-sc8180x
+ - qcom,pcie-sdm845
+ - qcom,pcie-sm8150
+ - qcom,pcie-sm8250
+ - qcom,pcie-sm8450-pcie0
+ - qcom,pcie-sm8450-pcie1
+ then:
+ oneOf:
+ - properties:
+ interrupts:
+ maxItems: 1
+ interrupt-names:
+ items:
+ - const: msi
+ - properties:
+ interrupts:
+ minItems: 8
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+ interrupt-names:
+ items:
+ - const: msi
+
unevaluatedProperties: false
examples:
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v16 5/6] dt-bindings: PCI: qcom: Support additional MSI interrupts
2022-07-04 15:27 ` [PATCH v16 5/6] dt-bindings: PCI: qcom: Support additional MSI interrupts Dmitry Baryshkov
@ 2022-07-07 8:06 ` Johan Hovold
2022-07-07 13:48 ` Dmitry Baryshkov
0 siblings, 1 reply; 14+ messages in thread
From: Johan Hovold @ 2022-07-07 8:06 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Manivannan Sadhasivam, Vinod Koul,
linux-arm-msm, linux-pci, devicetree, Krzysztof Kozlowski,
Rob Herring
On Mon, Jul 04, 2022 at 06:27:45PM +0300, Dmitry Baryshkov wrote:
> On Qualcomm platforms each group of 32 MSI vectors is routed to the
> separate GIC interrupt. Document mapping of additional interrupts.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../devicetree/bindings/pci/qcom,pcie.yaml | 51 +++++++++++++++++--
> 1 file changed, 48 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index c40ba753707c..ee5414522e3c 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -43,11 +43,12 @@ properties:
> maxItems: 5
>
> interrupts:
> - maxItems: 1
> + minItems: 1
> + maxItems: 8
>
> interrupt-names:
> - items:
> - - const: msi
> + minItems: 1
> + maxItems: 8
>
> # Common definitions for clocks, clock-names and reset.
> # Platform constraints are described later.
> @@ -623,6 +624,50 @@ allOf:
> - resets
> - reset-names
>
> + # On newer chipsets support either 1 or 8 msi interrupts
> + # On older chipsets it's always 1 msi interrupt
> + - if:
> + properties:
> + compatibles:
This still has the misspelled property name here (plural s) so the
conditional is always false.
I know I included a fix for this in my follow-on series, but if you are
respinning the series anyway you should fix it up.
> + contains:
> + enum:
> + - qcom,pcie-msm8996
> + - qcom,pcie-sc7280
> + - qcom,pcie-sc8180x
> + - qcom,pcie-sdm845
> + - qcom,pcie-sm8150
> + - qcom,pcie-sm8250
> + - qcom,pcie-sm8450-pcie0
> + - qcom,pcie-sm8450-pcie1
> + then:
> + oneOf:
> + - properties:
> + interrupts:
> + maxItems: 1
> + interrupt-names:
> + items:
> + - const: msi
> + - properties:
> + interrupts:
> + minItems: 8
> + interrupt-names:
> + items:
> + - const: msi0
> + - const: msi1
> + - const: msi2
> + - const: msi3
> + - const: msi4
> + - const: msi5
> + - const: msi6
> + - const: msi7
> + else:
> + properties:
> + interrupts:
> + maxItems: 1
> + interrupt-names:
> + items:
> + - const: msi
> +
> unevaluatedProperties: false
>
> examples:
Johan
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v16 5/6] dt-bindings: PCI: qcom: Support additional MSI interrupts
2022-07-07 8:06 ` Johan Hovold
@ 2022-07-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 14+ messages in thread
From: Dmitry Baryshkov @ 2022-07-07 13:48 UTC (permalink / raw)
To: Johan Hovold
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Manivannan Sadhasivam, Vinod Koul,
linux-arm-msm, linux-pci, devicetree, Krzysztof Kozlowski,
Rob Herring
On 07/07/2022 11:06, Johan Hovold wrote:
> On Mon, Jul 04, 2022 at 06:27:45PM +0300, Dmitry Baryshkov wrote:
>> On Qualcomm platforms each group of 32 MSI vectors is routed to the
>> separate GIC interrupt. Document mapping of additional interrupts.
>>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> .../devicetree/bindings/pci/qcom,pcie.yaml | 51 +++++++++++++++++--
>> 1 file changed, 48 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> index c40ba753707c..ee5414522e3c 100644
>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
[...]
>> @@ -623,6 +624,50 @@ allOf:
>> - resets
>> - reset-names
>>
>> + # On newer chipsets support either 1 or 8 msi interrupts
>> + # On older chipsets it's always 1 msi interrupt
>> + - if:
>> + properties:
>> + compatibles:
>
> This still has the misspelled property name here (plural s) so the
> conditional is always false.
>
> I know I included a fix for this in my follow-on series, but if you are
> respinning the series anyway you should fix it up.
Done, thanks a lot pointing me to it.
>
>> + contains:
>> + enum:
>> + - qcom,pcie-msm8996
[...]
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v16 6/6] arm64: dts: qcom: sm8250: provide additional MSI interrupts
2022-07-04 15:27 [PATCH v16 0/6] PCI: dwc: Fix higher MSI vectors handling Dmitry Baryshkov
` (4 preceding siblings ...)
2022-07-04 15:27 ` [PATCH v16 5/6] dt-bindings: PCI: qcom: Support additional MSI interrupts Dmitry Baryshkov
@ 2022-07-04 15:27 ` Dmitry Baryshkov
2022-07-04 16:46 ` Manivannan Sadhasivam
5 siblings, 1 reply; 14+ messages in thread
From: Dmitry Baryshkov @ 2022-07-04 15:27 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Manivannan Sadhasivam
Cc: Vinod Koul, linux-arm-msm, linux-pci, devicetree, Johan Hovold,
Johan Hovold
On SM8250 each group of MSI interrupts is mapped to the separate host
interrupt. Describe each of interrupts in the device tree for PCIe0
host.
Tested on Qualcomm RB5 platform with first group of MSI interrupts being
used by the PME and attached ath11k WiFi chip using second group of MSI
interrupts.
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 43c2d04b226f..3d7bfcb80ea0 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -1810,8 +1810,16 @@ pcie0: pci@1c00000 {
ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v16 6/6] arm64: dts: qcom: sm8250: provide additional MSI interrupts
2022-07-04 15:27 ` [PATCH v16 6/6] arm64: dts: qcom: sm8250: provide " Dmitry Baryshkov
@ 2022-07-04 16:46 ` Manivannan Sadhasivam
0 siblings, 0 replies; 14+ messages in thread
From: Manivannan Sadhasivam @ 2022-07-04 16:46 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Vinod Koul, linux-arm-msm, linux-pci,
devicetree, Johan Hovold, Johan Hovold
On Mon, Jul 04, 2022 at 06:27:46PM +0300, Dmitry Baryshkov wrote:
> On SM8250 each group of MSI interrupts is mapped to the separate host
> interrupt. Describe each of interrupts in the device tree for PCIe0
> host.
>
> Tested on Qualcomm RB5 platform with first group of MSI interrupts being
> used by the PME and attached ath11k WiFi chip using second group of MSI
> interrupts.
>
> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> ---
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index 43c2d04b226f..3d7bfcb80ea0 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -1810,8 +1810,16 @@ pcie0: pci@1c00000 {
> ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
> <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
>
> - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "msi";
> + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0", "msi1", "msi2", "msi3",
> + "msi4", "msi5", "msi6", "msi7";
> #interrupt-cells = <1>;
> interrupt-map-mask = <0 0 0 0x7>;
> interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> --
> 2.35.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 14+ messages in thread