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From: Rob Herring <robh@kernel.org>
To: Tinghan Shen <tinghan.shen@mediatek.com>
Cc: Yong Wu <yong.wu@mediatek.com>, Joerg Roedel <joro@8bytes.org>,
	Will Deacon <will@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Chun-Jie Chen <chun-jie.chen@mediatek.com>,
	AngeloGioacchino Del Regno 
	<angelogioacchino.delregno@collabora.com>,
	Enric Balletbo i Serra <enric.balletbo@collabora.com>,
	Weiyi Lu <weiyi.lu@mediatek.com>,
	iommu@lists.linux-foundation.org,
	linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH v1 03/16] dt-bindings: power: mediatek: Refine multiple level power domain nodes
Date: Tue, 5 Jul 2022 14:57:39 -0600	[thread overview]
Message-ID: <20220705205739.GA2599256-robh@kernel.org> (raw)
In-Reply-To: <20220704100028.19932-4-tinghan.shen@mediatek.com>

On Mon, Jul 04, 2022 at 06:00:15PM +0800, Tinghan Shen wrote:
> Extract duplicated properties and support more levels of power
> domain nodes.
> 
> This change fix following error when do dtbs_check,
>     arch/arm64/boot/dts/mediatek/mt8195-evb.dtb: power-controller: power-domain@15:power-domain@16:power-domain@18: 'power-domain@19', 'power-domain@20', 'power-domain@21' do not match any of the regexes: 'pinctrl-[0-9]+'
> 	 From schema: Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> 
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
>  .../power/mediatek,power-controller.yaml      | 132 ++----------------
>  1 file changed, 12 insertions(+), 120 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> index 135c6f722091..09a537a802b8 100644
> --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> @@ -39,8 +39,17 @@ properties:
>    '#size-cells':
>      const: 0
>  
> +required:
> +  - compatible
> +
> +additionalProperties: false
> +
>  patternProperties:
>    "^power-domain@[0-9a-f]+$":
> +    $ref: "#/$defs/power-domain-node"
> +
> +$defs:
> +  power-domain-node:
>      type: object
>      description: |
>        Represents the power domains within the power controller node as documented
> @@ -98,127 +107,10 @@ patternProperties:
>          $ref: /schemas/types.yaml#/definitions/phandle
>          description: phandle to the device containing the SMI register range.
>  
> -    patternProperties:
> -      "^power-domain@[0-9a-f]+$":
> -        type: object
> -        description: |
> -          Represents a power domain child within a power domain parent node.
> -
> -        properties:
> -
> -          '#power-domain-cells':
> -            description:
> -              Must be 0 for nodes representing a single PM domain and 1 for nodes
> -              providing multiple PM domains.
> -
> -          '#address-cells':
> -            const: 1
> -
> -          '#size-cells':
> -            const: 0
> -
> -          reg:
> -            maxItems: 1
> -
> -          clocks:
> -            description: |
> -              A number of phandles to clocks that need to be enabled during domain
> -              power-up sequencing.
> -
> -          clock-names:
> -            description: |
> -              List of names of clocks, in order to match the power-up sequencing
> -              for each power domain we need to group the clocks by name. BASIC
> -              clocks need to be enabled before enabling the corresponding power
> -              domain, and should not have a '-' in their name (i.e mm, mfg, venc).
> -              SUSBYS clocks need to be enabled before releasing the bus protection,
> -              and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
> -
> -              In order to follow properly the power-up sequencing, the clocks must
> -              be specified by order, adding first the BASIC clocks followed by the
> -              SUSBSYS clocks.
> -
> -          domain-supply:
> -            description: domain regulator supply.
> -
> -          mediatek,infracfg:
> -            $ref: /schemas/types.yaml#/definitions/phandle
> -            description: phandle to the device containing the INFRACFG register range.
> -
> -          mediatek,smi:
> -            $ref: /schemas/types.yaml#/definitions/phandle
> -            description: phandle to the device containing the SMI register range.
> -
> -        patternProperties:
> -          "^power-domain@[0-9a-f]+$":
> -            type: object
> -            description: |
> -              Represents a power domain child within a power domain parent node.
> -
> -            properties:
> +      required:
> +        - reg
>  
> -              '#power-domain-cells':
> -                description:
> -                  Must be 0 for nodes representing a single PM domain and 1 for nodes
> -                  providing multiple PM domains.
> -
> -              '#address-cells':
> -                const: 1
> -
> -              '#size-cells':
> -                const: 0
> -
> -              reg:
> -                maxItems: 1
> -
> -              clocks:
> -                description: |
> -                  A number of phandles to clocks that need to be enabled during domain
> -                  power-up sequencing.
> -
> -              clock-names:
> -                description: |
> -                  List of names of clocks, in order to match the power-up sequencing
> -                  for each power domain we need to group the clocks by name. BASIC
> -                  clocks need to be enabled before enabling the corresponding power
> -                  domain, and should not have a '-' in their name (i.e mm, mfg, venc).
> -                  SUSBYS clocks need to be enabled before releasing the bus protection,
> -                  and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
> -
> -                  In order to follow properly the power-up sequencing, the clocks must
> -                  be specified by order, adding first the BASIC clocks followed by the
> -                  SUSBSYS clocks.
> -
> -              domain-supply:
> -                description: domain regulator supply.
> -
> -              mediatek,infracfg:
> -                $ref: /schemas/types.yaml#/definitions/phandle
> -                description: phandle to the device containing the INFRACFG register range.
> -
> -              mediatek,smi:
> -                $ref: /schemas/types.yaml#/definitions/phandle
> -                description: phandle to the device containing the SMI register range.
> -
> -            required:
> -              - reg
> -
> -            additionalProperties: false
> -
> -        required:
> -          - reg
> -
> -        additionalProperties: false
> -
> -    required:
> -      - reg
> -
> -    additionalProperties: false
> -
> -required:
> -  - compatible
> -
> -additionalProperties: false
> +      additionalProperties: false

You now aren't checking more than 1 level because you have defined 
'additionalProperties' to be a DT property. Check the indentation.

You need this in $defs/power-domain-node to recurse:

    additionalProperties:
      $ref: #/$defs/power-domain-node

>  
>  examples:
>    - |
> -- 
> 2.18.0
> 
> 

  reply	other threads:[~2022-07-05 20:57 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-04 10:00 [PATCH v1 00/16] Add driver nodes for MT8195 SoC Tinghan Shen
2022-07-04 10:00 ` [PATCH v1 01/16] dt-bindings: iommu: mediatek: Increase max interrupt number Tinghan Shen
2022-07-05 20:49   ` Rob Herring
2022-07-06  4:03     ` Tinghan Shen
2022-07-04 10:00 ` [PATCH v1 02/16] dt-bindings: memory: mediatek: Update condition for mt8195 smi node Tinghan Shen
2022-07-04 10:25   ` AngeloGioacchino Del Regno
2022-07-06  3:59     ` Tinghan Shen
2022-07-04 12:36   ` Krzysztof Kozlowski
2022-07-06  4:01     ` Tinghan Shen
2022-07-06 13:48     ` Matthias Brugger
2022-07-06 14:38       ` Krzysztof Kozlowski
2022-07-07 13:02         ` Matthias Brugger
2022-07-04 10:00 ` [PATCH v1 03/16] dt-bindings: power: mediatek: Refine multiple level power domain nodes Tinghan Shen
2022-07-05 20:57   ` Rob Herring [this message]
2022-07-06  6:19     ` Tinghan Shen
2022-07-12 19:21       ` Rob Herring
2022-07-14 12:22         ` Tinghan Shen
2022-07-04 10:00 ` [PATCH v1 04/16] arm64: dts: mt8195: Disable watchdog external reset signal Tinghan Shen
2022-07-04 10:30   ` AngeloGioacchino Del Regno
2022-07-06  4:00     ` Tinghan Shen
2022-07-04 10:00 ` [PATCH v1 05/16] arm64: dts: mt8195: Disable I2C0 node Tinghan Shen
2022-07-04 10:33   ` AngeloGioacchino Del Regno
2022-07-04 10:00 ` [PATCH v1 06/16] arm64: dts: mt8195: Add cpufreq node Tinghan Shen
2022-07-04 10:41   ` AngeloGioacchino Del Regno
2022-07-04 10:00 ` [PATCH v1 07/16] arm64: dts: mt8195: Add vdosys and vppsys clock nodes Tinghan Shen
2022-07-04 10:41   ` AngeloGioacchino Del Regno
2022-07-04 10:00 ` [PATCH v1 08/16] arm64: dts: mt8195: Add power domains controller Tinghan Shen
2022-07-04 10:41   ` AngeloGioacchino Del Regno
2022-07-04 12:38   ` Krzysztof Kozlowski
2022-07-06 12:00     ` Tinghan Shen
2022-07-06 15:18       ` Krzysztof Kozlowski
2022-07-12  8:17         ` AngeloGioacchino Del Regno
2022-07-12  8:37           ` Krzysztof Kozlowski
2022-07-12  8:53             ` AngeloGioacchino Del Regno
2022-07-12  9:03               ` Krzysztof Kozlowski
2022-07-12 10:33                 ` AngeloGioacchino Del Regno
2022-07-12 12:47                   ` Krzysztof Kozlowski
2022-07-12 12:54                     ` AngeloGioacchino Del Regno
2022-07-12 12:58                       ` Krzysztof Kozlowski
2022-07-12 13:03                         ` AngeloGioacchino Del Regno
2022-07-12 13:30                           ` Krzysztof Kozlowski
2022-07-06 13:41     ` Matthias Brugger
2022-07-06 14:35       ` Krzysztof Kozlowski
2022-07-04 10:00 ` [PATCH v1 09/16] arm64: dts: mt8195: Add spmi node Tinghan Shen
2022-07-04 10:41   ` AngeloGioacchino Del Regno
2022-07-04 10:00 ` [PATCH v1 10/16] arm64: dts: mt8195: Add scp node Tinghan Shen
2022-07-04 10:41   ` AngeloGioacchino Del Regno
2022-07-04 10:00 ` [PATCH v1 11/16] arm64: dts: mt8195: Add audio related nodes Tinghan Shen
2022-07-04 10:41   ` AngeloGioacchino Del Regno
2022-07-04 10:00 ` [PATCH v1 12/16] arm64: dts: mt8195: Add adsp node and adsp mailbox nodes Tinghan Shen
2022-07-04 10:00 ` [PATCH v1 13/16] arm64: dts: mt8195: Specify audio reset controller Tinghan Shen
2022-07-04 10:40   ` AngeloGioacchino Del Regno
2022-07-04 10:00 ` [PATCH v1 14/16] arm64: dts: mt8195: Add iommu and smi nodes Tinghan Shen
2022-07-04 10:40   ` AngeloGioacchino Del Regno
     [not found] ` <20220704100028.19932-16-tinghan.shen@mediatek.com>
2022-07-04 10:41   ` [PATCH v1 15/16] arm64: dts: mt8195: Add gce node AngeloGioacchino Del Regno
     [not found] ` <20220704100028.19932-17-tinghan.shen@mediatek.com>
2022-07-04 10:44   ` [PATCH v1 16/16] arm64: dts: mt8195: Add display node for vdosys0 AngeloGioacchino Del Regno
2022-07-04 12:39   ` Krzysztof Kozlowski

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