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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id fi18-20020a056402551200b0043a43fcde13sm7711033edb.13.2022.07.06.08.43.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 08:43:48 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jonathan@marek.ca, robert.foss@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Vinod Koul Subject: [PATCH v8 5/5] arm64: dts: qcom: sm8350: Add DISPCC node Date: Wed, 6 Jul 2022 17:43:37 +0200 Message-Id: <20220706154337.2026269-6-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220706154337.2026269-1-robert.foss@linaro.org> References: <20220706154337.2026269-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the dispcc clock-controller DT node for sm8350. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- Changes since v2 - Remove interconnect include - Bjorn Changes since v3 - Switch from .fw_name to .index Changes since v5 - Revert .fw_name to .index change Changes since v6 - Add r-b - Konrad arch/arm64/boot/dts/qcom/sm8350.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 447a02f10463..aa0ca45ca184 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -2531,6 +2532,31 @@ usb_2_dwc3: usb@a800000 { }; }; + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8350-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + power-domains = <&rpmhpd SM8350_MMCX>; + power-domain-names = "mmcx"; + }; + adsp: remoteproc@17300000 { compatible = "qcom,sm8350-adsp-pas"; reg = <0 0x17300000 0 0x100>; -- 2.34.1