From: Conor Dooley <conor.dooley@microchip.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
"Lee Jones" <lee.jones@linaro.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>
Cc: Daire McNamara <daire.mcnamara@microchip.com>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-pwm@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v5 0/4] Microchip soft ip corePWM driver
Date: Fri, 8 Jul 2022 15:39:19 +0100 [thread overview]
Message-ID: <20220708143923.1129928-1-conor.dooley@microchip.com> (raw)
Hey Uwe, all,
Added some extra patches so I have a cover letter this time.
You pointed out that I was overriding npwmcells in the driver and I
realised that the dt & binding were not correct so I have added two
simple patches to deal with that. The dts patch I will take in my tree
once the binding is applied.
For the maintainers entry, I mentioned before that I have several
changes in-flight for it. We are late(ish) in the cycle so I doubt
you'll be applying this for v5.20, but in the off chance you do - I
would be happy to send it (with your Ack) alongside an i2c addition
that is "deferred".
In your review of v3, you had a lot of comments about the period and
duty cycle calculations, so I have had another run at them. I converted
the period calculation to "search" from the bottom up for the suitable
prescale value. The duty cycle calculation has been fixed - the problem
was exactly what I suspected in my replies to your review. I had to block
the use of a 0xFF period_steps register value (which I think should be
covered by the updated comment and limitation #2).
Beyond that, I have rebased on -next and converted to the devm_ stuff
in probe that was recently added & dropped remove() - as requested.
I added locking to protect the period racing, changed the #defines and
switched to returning -EINVAL when the period is locked to a value
greater than that requested.
Thanks,
Conor.
Changes from v4:
- dropped some accidentally added files
Conor Dooley (4):
dt-bindings: pwm: fix microchip corePWM's pwm-cells
riscv: dts: fix the icicle's #pwm-cells
pwm: add microchip soft ip corePWM driver
MAINTAINERS: add pwm to PolarFire SoC entry
.../bindings/pwm/microchip,corepwm.yaml | 4 +-
MAINTAINERS | 1 +
.../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +-
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-microchip-core.c | 355 ++++++++++++++++++
6 files changed, 371 insertions(+), 2 deletions(-)
create mode 100644 drivers/pwm/pwm-microchip-core.c
base-commit: 088b9c375534d905a4d337c78db3b3bfbb52c4a0
--
2.36.1
next reply other threads:[~2022-07-08 14:39 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-08 14:39 Conor Dooley [this message]
2022-07-08 14:39 ` [PATCH v5 1/4] dt-bindings: pwm: fix microchip corePWM's pwm-cells Conor Dooley
2022-07-11 23:06 ` Rob Herring
2022-07-08 14:39 ` [PATCH v5 2/4] riscv: dts: fix the icicle's #pwm-cells Conor Dooley
2022-07-08 14:39 ` [PATCH v5 3/4] pwm: add microchip soft ip corePWM driver Conor Dooley
2022-07-09 16:02 ` Uwe Kleine-König
2022-07-09 16:21 ` Conor.Dooley
2022-07-09 16:37 ` Uwe Kleine-König
2022-07-09 16:56 ` Conor.Dooley
2022-07-11 14:33 ` Conor.Dooley
2022-07-12 10:57 ` Conor.Dooley
2022-07-08 14:39 ` [PATCH v5 4/4] MAINTAINERS: add pwm to PolarFire SoC entry Conor Dooley
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