From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D1BFCCA47C for ; Sat, 9 Jul 2022 08:01:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229505AbiGIIBI (ORCPT ); Sat, 9 Jul 2022 04:01:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229379AbiGIIBG (ORCPT ); Sat, 9 Jul 2022 04:01:06 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62B6070993 for ; Sat, 9 Jul 2022 01:01:04 -0700 (PDT) Received: by mail-pj1-x102c.google.com with SMTP id i8-20020a17090a4b8800b001ef8a65bfbdso636372pjh.1 for ; Sat, 09 Jul 2022 01:01:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to; bh=Kv2xJstIHFNMVTi9JObJDGpbOPxYWB6plwIYntYZfnU=; b=hT7PdxzrgY4kMYwSPZVvWBwVaMEUe07GcOlkS0BW2Zim6pVS9k01bQBFO/1zxpeJJf WoCuCHnWD4Co9hA/VtKmddftYXp1OesZlPj+wPL91leKm1IDbVUGvDssH6/P5sFlaK4K ykAGvX0aZHryLfE4ICOoSyE7OueMijWR23AjRJiiElyoK4dwda1SY0XmDbvsPRgucR/v 6Aq25yX8bZ0leaZf75sx9v8V6YWPPNhnEKP3/R9I8/4dGQ71d/v3hhQpRRTpQnhtwxNN fOyA19ytLilWESJnY8g+ASvrupaLDcWTFaFcIHEueC3boWSzyziLH7Ibs7bpomsPafQb tQ5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=Kv2xJstIHFNMVTi9JObJDGpbOPxYWB6plwIYntYZfnU=; b=BEz8g6bu9lN6whuJHW3ddZ4+2AGL0E+F0m/4McNLB7uq/GXpMza0TohNTCRSRy2Gu5 +R8lztxbG+hArjGtBDT1zYQhxx1qubnFaFPYBjLxCBS//33dBBMWbUUmxHvCQQv9AhQ3 uVtASwVJCLB5qkFqZ6DxdoQrzjDpfLnd1sgqW3ILcG7qYSY2IV8xPD7SHJhYjm8ri9Kz 1uG7J1+OPk7snC3alAMoedO9QG6PS0BZQkY5OvMSufMBUr5BVfpglJYz+2UW8tfzGovX YXAi5sXI1VxV/M+3yW6ZeybzxhRdl/t+bAKGRbiHFLqpVOEVlQpP/lh+pwEVWHb0EeNU XPPQ== X-Gm-Message-State: AJIora+R5dCs5cqscQVZLf6itlJv0ggMxWaP6URLtTssK+I1WJtghZfP Po1B1JO1ZZIuyxx2oUeEY4Tb X-Google-Smtp-Source: AGRyM1t6ezElgdxxHGRnMkuUkUoVzAQGBgNEEykjrteiLAautAVsJn4UFw4R9UDVM0fFvlDU7XBl5Q== X-Received: by 2002:a17:902:9041:b0:16a:aef:7b84 with SMTP id w1-20020a170902904100b0016a0aef7b84mr7929453plz.124.1657353663842; Sat, 09 Jul 2022 01:01:03 -0700 (PDT) Received: from thinkpad ([117.207.26.140]) by smtp.gmail.com with ESMTPSA id c2-20020a170902d48200b0016bc947c5b7sm761888plg.38.2022.07.09.01.00.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Jul 2022 01:01:03 -0700 (PDT) Date: Sat, 9 Jul 2022 13:30:53 +0530 From: Manivannan Sadhasivam To: Johan Hovold Cc: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski , Stanimir Varbanov , Andy Gross , Bjorn Andersson , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 04/10] dt-bindings: PCI: qcom: Add SC8280XP to binding Message-ID: <20220709080053.GK5063@thinkpad> References: <20220629141000.18111-1-johan+linaro@kernel.org> <20220629141000.18111-5-johan+linaro@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220629141000.18111-5-johan+linaro@kernel.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Jun 29, 2022 at 04:09:54PM +0200, Johan Hovold wrote: > Add the SC8280XP platform to the binding. > > SC8280XP use four host interrupts for MSI routing so remove the obsolete > comment referring to newer chipsets supporting one or eight interrupts > (e.g. for backwards compatibility). > > Signed-off-by: Johan Hovold Wondering why 4 on this SoC. Is this what added in downstream or you also verified it with IP documentation. Thanks, Mani > --- > .../devicetree/bindings/pci/qcom,pcie.yaml | 50 ++++++++++++++++++- > 1 file changed, 49 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index 8560c65e6f0b..a039f6110322 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -27,6 +27,7 @@ properties: > - qcom,pcie-qcs404 > - qcom,pcie-sc7280 > - qcom,pcie-sc8180x > + - qcom,pcie-sc8280xp > - qcom,pcie-sdm845 > - qcom,pcie-sm8150 > - qcom,pcie-sm8250 > @@ -181,6 +182,7 @@ allOf: > enum: > - qcom,pcie-sc7280 > - qcom,pcie-sc8180x > + - qcom,pcie-sc8280xp > - qcom,pcie-sm8250 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > @@ -596,6 +598,35 @@ allOf: > items: > - const: pci # PCIe core reset > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-sc8280xp > + then: > + properties: > + clocks: > + minItems: 8 > + maxItems: 9 > + clock-names: > + minItems: 8 > + items: > + - const: aux # Auxiliary clock > + - const: cfg # Configuration clock > + - const: bus_master # Master AXI clock > + - const: bus_slave # Slave AXI clock > + - const: slave_q2a # Slave Q2A clock > + - const: ddrss_sf_tbu # PCIe SF TBU clock > + - const: noc_aggr_4 # NoC aggregate 4 clock > + - const: noc_aggr_south_sf # NoC aggregate South SF clock > + - const: cnoc_qx # Configuration NoC QX clock > + resets: > + maxItems: 1 > + reset-names: > + items: > + - const: pci # PCIe core reset > + > - if: > not: > properties: > @@ -624,7 +655,6 @@ allOf: > - resets > - reset-names > > - # On newer chipsets support either 1 or 8 msi interrupts > - if: > properties: > compatible: > @@ -660,6 +690,24 @@ allOf: > - const: msi6 > - const: msi7 > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-sc8280xp > + then: > + properties: > + interrupts: > + minItems: 4 > + maxItems: 4 > + interrupt-names: > + items: > + - const: msi0 > + - const: msi1 > + - const: msi2 > + - const: msi3 > + > - if: > properties: > compatible: > -- > 2.35.1 > -- மணிவண்ணன் சதாசிவம்