From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F0DFCCA480 for ; Sat, 9 Jul 2022 08:25:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229477AbiGIIZU (ORCPT ); Sat, 9 Jul 2022 04:25:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229482AbiGIIZT (ORCPT ); Sat, 9 Jul 2022 04:25:19 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D43BC76EAC for ; Sat, 9 Jul 2022 01:25:17 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id fz10so912906pjb.2 for ; Sat, 09 Jul 2022 01:25:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to; bh=/Sx0YWTOU70ldR3qqRLiimjlPwcJ9/ZDdFLcC6JdMgc=; b=GFukNcWocDEKQ8p1Vr7y9wt8wzLNjfnf3r0mCzRBEbpO+N4nhKVlsoBIlYgNke4OIE kcN6ptLfXPAuhhRQWeEmyLZMaXmJQEuPxHfh5V2uuBPE51gtC7yJOPm5/zFqTrKUiDiG J7BxP0bL80mby6CoXKv91M6+/96Ye4vJ/JI9oza8IWlK/+q3LXFfU8c6EYsY29imoStr XAGmZu19TYrQHd+p3RoyQ4FomGPbjMfLwAv8M8TKx207RxpRLRTdR21KbT/EnLmZ9nNT wKlGglJxQRWf7Gm3LnO/W1+KASmkj190IoIy/ztV1fVJdemmOZYwJ4ZVSs+gjJm/+bIn 8bug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=/Sx0YWTOU70ldR3qqRLiimjlPwcJ9/ZDdFLcC6JdMgc=; b=EtunVvapU7D9+1plPCutm1Z77PGbMyTDfgKnkhqz4y0zp5k/pVRnx4QzWelHtklFLE hHEJmCrjRM4mktefPFLsOC0CxgQ/zSaiaVoeRjVyAzULic2LtpcAJeMyXVQMv0Nr/zjk 2j/XVxgctsrLcvG+CVM9sOS4o0Fp3frWA0jzC3s3V/tT2W93le4pr/pS/Dwydbe9rk2V VnMfwlo8+2RkiYcBdafRQ5h0BcT20R2t1TWzmGnnsA2E9s0drMLItk4zapjS728EqXvO hkDlatatucTGrXUySY4ow8cHANOyHilRoVP5iWJFkdU5fnKKP2Rw6fyFvKqcRxmHDMlc vTWg== X-Gm-Message-State: AJIora/80mnG5AmbffEFrtp8YeiYFCsD1U+aftfeKtPjrUUupWWyd7pF W7alyoHzqhceN39EYGpYbc5K X-Google-Smtp-Source: AGRyM1ufOWTPz98QGa9I0QzB1DRe7WPSkiwMrjR3T/xAs6zT96KF64La56lHoPYR55s6Ev1/9xDfxA== X-Received: by 2002:a17:90b:4ac1:b0:1ef:c1ba:e73e with SMTP id mh1-20020a17090b4ac100b001efc1bae73emr4717331pjb.47.1657355117339; Sat, 09 Jul 2022 01:25:17 -0700 (PDT) Received: from thinkpad ([117.207.26.140]) by smtp.gmail.com with ESMTPSA id u188-20020a6260c5000000b0050dc7628183sm939074pfb.93.2022.07.09.01.25.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Jul 2022 01:25:17 -0700 (PDT) Date: Sat, 9 Jul 2022 13:55:09 +0530 From: Manivannan Sadhasivam To: Johan Hovold Cc: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski , Stanimir Varbanov , Andy Gross , Bjorn Andersson , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 09/10] PCI: qcom: Clean up IP configurations Message-ID: <20220709082509.GP5063@thinkpad> References: <20220629141000.18111-1-johan+linaro@kernel.org> <20220629141000.18111-10-johan+linaro@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220629141000.18111-10-johan+linaro@kernel.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Jun 29, 2022 at 04:09:59PM +0200, Johan Hovold wrote: > The various IP versions have different configurations that are encoded > in separate sets of operation callbacks. Currently, there is no need for > also maintaining corresponding sets of data parameters, but it is > conceivable that these may again be found useful (e.g. to implement > minor variations of the operation callbacks). > > Rename the default configuration structures after the IP version they > apply to so that they can more easily be reused by different SoCs. > > Note that SoC specific configurations can be added later if need arises > (e.g. cfg_sc8280xp). > > Signed-off-by: Johan Hovold Reviewed-by: Manivannan Sadhasivam Thanks, Mani > --- > drivers/pci/controller/dwc/pcie-qcom.c | 85 ++++++++------------------ > 1 file changed, 27 insertions(+), 58 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 1a564f624bb1..567601679465 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1433,65 +1433,34 @@ static const struct qcom_pcie_ops ops_1_9_0 = { > .config_sid = qcom_pcie_config_sid_sm8250, > }; > > -static const struct qcom_pcie_cfg apq8084_cfg = { > +static const struct qcom_pcie_cfg cfg_1_0_0 = { > .ops = &ops_1_0_0, > }; > > -static const struct qcom_pcie_cfg ipq8064_cfg = { > +static const struct qcom_pcie_cfg cfg_1_9_0 = { > + .ops = &ops_1_9_0, > +}; > + > +static const struct qcom_pcie_cfg cfg_2_1_0 = { > .ops = &ops_2_1_0, > }; > > -static const struct qcom_pcie_cfg msm8996_cfg = { > +static const struct qcom_pcie_cfg cfg_2_3_2 = { > .ops = &ops_2_3_2, > }; > > -static const struct qcom_pcie_cfg ipq8074_cfg = { > +static const struct qcom_pcie_cfg cfg_2_3_3 = { > .ops = &ops_2_3_3, > }; > > -static const struct qcom_pcie_cfg ipq4019_cfg = { > +static const struct qcom_pcie_cfg cfg_2_4_0 = { > .ops = &ops_2_4_0, > }; > > -static const struct qcom_pcie_cfg sa8540p_cfg = { > - .ops = &ops_1_9_0, > -}; > - > -static const struct qcom_pcie_cfg sc8280xp_cfg = { > - .ops = &ops_1_9_0, > -}; > - > -static const struct qcom_pcie_cfg sdm845_cfg = { > +static const struct qcom_pcie_cfg cfg_2_7_0 = { > .ops = &ops_2_7_0, > }; > > -static const struct qcom_pcie_cfg sm8150_cfg = { > - /* sm8150 has qcom IP rev 1.5.0. However 1.5.0 ops are same as > - * 1.9.0, so reuse the same. > - */ > - .ops = &ops_1_9_0, > -}; > - > -static const struct qcom_pcie_cfg sm8250_cfg = { > - .ops = &ops_1_9_0, > -}; > - > -static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { > - .ops = &ops_1_9_0, > -}; > - > -static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { > - .ops = &ops_1_9_0, > -}; > - > -static const struct qcom_pcie_cfg sc7280_cfg = { > - .ops = &ops_1_9_0, > -}; > - > -static const struct qcom_pcie_cfg sc8180x_cfg = { > - .ops = &ops_1_9_0, > -}; > - > static const struct dw_pcie_ops dw_pcie_ops = { > .link_up = qcom_pcie_link_up, > .start_link = qcom_pcie_start_link, > @@ -1603,23 +1572,23 @@ static int qcom_pcie_remove(struct platform_device *pdev) > } > > static const struct of_device_id qcom_pcie_match[] = { > - { .compatible = "qcom,pcie-apq8084", .data = &apq8084_cfg }, > - { .compatible = "qcom,pcie-ipq8064", .data = &ipq8064_cfg }, > - { .compatible = "qcom,pcie-ipq8064-v2", .data = &ipq8064_cfg }, > - { .compatible = "qcom,pcie-apq8064", .data = &ipq8064_cfg }, > - { .compatible = "qcom,pcie-msm8996", .data = &msm8996_cfg }, > - { .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg }, > - { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg }, > - { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg }, > - { .compatible = "qcom,pcie-sa8540p", .data = &sa8540p_cfg }, > - { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, > - { .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg }, > - { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, > - { .compatible = "qcom,pcie-sc8180x", .data = &sc8180x_cfg }, > - { .compatible = "qcom,pcie-sc8280xp", .data = &sc8280xp_cfg }, > - { .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg }, > - { .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg }, > - { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg }, > + { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 }, > + { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 }, > + { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, > + { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 }, > + { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, > + { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 }, > + { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 }, > + { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, > + { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 }, > + { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 }, > + { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 }, > + { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 }, > + { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 }, > + { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 }, > + { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, > + { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, > + { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 }, > { } > }; > MODULE_DEVICE_TABLE(of, qcom_pcie_match); > -- > 2.35.1 > -- மணிவண்ணன் சதாசிவம்