[PATCH 1/5] dt-bindings: arm: tegra: flowctrl: Convert to json-schema

[PATCH 1/5] dt-bindings: arm: tegra: flowctrl: Convert to json-schema

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Convert the Tegra flow controller bindings from the free-form text
format to json-schema.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../arm/tegra/nvidia,tegra20-flowctrl.txt     | 18 --------
 .../arm/tegra/nvidia,tegra20-flowctrl.yaml    | 41 +++++++++++++++++++
 2 files changed, 41 insertions(+), 18 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
 create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.yaml

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
deleted file mode 100644
index a855c1bffc0f..000000000000
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-NVIDIA Tegra Flow Controller
-
-Required properties:
-- compatible: Should contain one of the following:
-  - "nvidia,tegra20-flowctrl": for Tegra20
-  - "nvidia,tegra30-flowctrl": for Tegra30
-  - "nvidia,tegra114-flowctrl": for Tegra114
-  - "nvidia,tegra124-flowctrl": for Tegra124
-  - "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl": for Tegra132
-  - "nvidia,tegra210-flowctrl": for Tegra210
-- reg: Should contain one register range (address and length)
-
-Example:
-
-	flow-controller@60007000 {
-		compatible = "nvidia,tegra20-flowctrl";
-		reg = <0x60007000 0x1000>;
-	};
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.yaml
new file mode 100644
index 000000000000..416739ad8c1e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-flowctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Flow Controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - nvidia,tegra20-flowctrl
+          - nvidia,tegra30-flowctrl
+          - nvidia,tegra114-flowctrl
+          - nvidia,tegra124-flowctrl
+          - nvidia,tegra210-flowctrl
+
+      - items:
+          - const: nvidia,tegra132-flowctrl
+          - const: nvidia,tegra124-flowctrl
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    flow-controller@60007000 {
+        compatible = "nvidia,tegra20-flowctrl";
+        reg = <0x60007000 0x1000>;
+    };
-- 
2.36.1

[PATCH 2/5] dt-bindings: arm: tegra: ahb: Convert to json-schema

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Convert the NVIDIA Tegra AHB bindings from the free-form text format to
json-schema.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../bindings/arm/tegra/nvidia,tegra20-ahb.txt | 17 --------
 .../arm/tegra/nvidia,tegra20-ahb.yaml         | 39 +++++++++++++++++++
 2 files changed, 39 insertions(+), 17 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt
 create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.yaml

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt
deleted file mode 100644
index 9a4295b54539..000000000000
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-NVIDIA Tegra AHB
-
-Required properties:
-- compatible : For Tegra20, must contain "nvidia,tegra20-ahb".  For
-  Tegra30, must contain "nvidia,tegra30-ahb".  Otherwise, must contain
-  '"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,
-  tegra132, or tegra210.
-- reg : Should contain 1 register ranges(address and length).  For
-  Tegra20, Tegra30, and Tegra114 chips, the value must be <0x6000c004
-  0x10c>.  For Tegra124, Tegra132 and Tegra210 chips, the value should
-  be be <0x6000c000 0x150>.
-
-Example (for a Tegra20 chip):
-	ahb: ahb@6000c004 {
-		compatible = "nvidia,tegra20-ahb";
-		reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
-	};
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.yaml
new file mode 100644
index 000000000000..6d9baab76258
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-ahb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+title: NVIDIA Tegra AHB
+
+properties:
+  compatible:
+    oneOf:
+      - const: nvidia,tegra20-ahb
+      - const: nvidia,tegra30-ahb
+      - items:
+          - enum:
+              - nvidia,tegra114-ahb
+              - nvidia,tegra124-ahb
+              - nvidia,tegra210-ahb
+          - const: nvidia,tegra30-ahb
+
+  reg:
+    maxItems: 1
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    ahb@6000c004 {
+      compatible = "nvidia,tegra20-ahb";
+      reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
+    };
-- 
2.36.1

[PATCH 3/5] dt-bindings: arm: tegra: nvec: Convert to json-schema

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Convert the NVIDIA embedded controller bindings from the free-form text
format to json-schema.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Marc,

you authored this binding a long time ago, which makes the default
license for this GPL-2.0. However, the preference is for DT bindings to
be dual-licensed under the more permissive GPL-2.0-only OR BSD-2-Clause
as done in this patch. Do you have any objections to relicensing?

Thierry

 .../bindings/arm/tegra/nvidia,nvec.txt        | 21 -----
 .../bindings/arm/tegra/nvidia,nvec.yaml       | 94 +++++++++++++++++++
 2 files changed, 94 insertions(+), 21 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt
 create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.yaml

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt
deleted file mode 100644
index 5ae601e7f51f..000000000000
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-NVIDIA compliant embedded controller
-
-Required properties:
-- compatible : should be "nvidia,nvec".
-- reg : the iomem of the i2c slave controller
-- interrupts : the interrupt line of the i2c slave controller
-- clock-frequency : the frequency of the i2c bus
-- gpios : the gpio used for ec request
-- slave-addr: the i2c address of the slave controller
-- clocks : Must contain an entry for each entry in clock-names.
-  See ../clocks/clock-bindings.txt for details.
-- clock-names : Must include the following entries:
-  Tegra20/Tegra30:
-  - div-clk
-  - fast-clk
-  Tegra114:
-  - div-clk
-- resets : Must contain an entry for each entry in reset-names.
-  See ../reset/reset.txt for details.
-- reset-names : Must include the following entries:
-  - i2c
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.yaml
new file mode 100644
index 000000000000..c997faa42c31
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/tegra/nvidia,nvec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA compliant embedded controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  compatible:
+    const: nvidia,nvec
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    items:
+      - description: divider clock
+      - description: fast clock
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: div-clk
+      - const: fast-clk
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: i2c
+
+  clock-frequency:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: frequency of the I2C bus
+
+  request-gpios:
+    description: phandle to the GPIO used for EC request
+
+  slave-addr:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: I2C address of the slave controller
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - clock-frequency
+  - request-gpios
+  - slave-addr
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/gpio/tegra-gpio.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    nvec@7000c500 {
+      compatible = "nvidia,nvec";
+      reg = <0x7000c500 0x100>;
+      interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+      #address-cells = <1>;
+      #size-cells = <0>;
+      clock-frequency = <80000>;
+      request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+      slave-addr = <138>;
+      clocks = <&tegra_car TEGRA20_CLK_I2C3>,
+               <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
+      clock-names = "div-clk", "fast-clk";
+      resets = <&tegra_car 67>;
+      reset-names = "i2c";
+    };
-- 
2.36.1

[PATCH 4/5] dt-bindings: arm: tegra: Revise Tegra20 PMC bindings

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Update the Tegra20 PMC bindings to make use of some advanced json-schema
features such as describing list elements or validating the contents of
string arrays.

While at it, also restructure the pad configuration node schema to make
sure it doesn't accidentally match other properties.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../arm/tegra/nvidia,tegra20-pmc.yaml         | 512 ++++++++++--------
 1 file changed, 282 insertions(+), 230 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index 564ae6aaccf7..6894addb3c9a 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
@@ -21,141 +21,134 @@ properties:
 
   reg:
     maxItems: 1
-    description:
-      Offset and length of the register set for the device.
+    description: Offset and length of the register set for the device.
 
   clock-names:
     items:
       - const: pclk
       - const: clk32k_in
-    description:
-      Must includes entries pclk and clk32k_in.
-      pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
-      input to Tegra.
+    description: Must includes entries pclk and clk32k_in. pclk is the Tegra
+      clock of that name and clk32k_in is 32KHz clock input to Tegra.
 
   clocks:
     maxItems: 2
-    description:
-      Must contain an entry for each entry in clock-names.
-      See ../clocks/clocks-bindings.txt for details.
+    description: Must contain an entry for each entry in clock-names. See
+      ../clocks/clocks-bindings.txt for details.
 
   '#clock-cells':
     const: 1
-    description:
-      Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
-      PMC also has blink control which allows 32Khz clock output to
-      Tegra blink pad.
-      Consumer of PMC clock should specify the desired clock by having
-      the clock ID in its "clocks" phandle cell with pmc clock provider.
-      See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
-      clock IDs.
+    description: |
+      Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. PMC also has blink
+      control which allows 32Khz clock output to Tegra blink pad.
+
+      Consumer of PMC clock should specify the desired clock by having the
+      clock ID in its "clocks" phandle cell with PMC clock provider. See
+      include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC clock IDs.
 
   '#interrupt-cells':
     const: 2
-    description:
-      Specifies number of cells needed to encode an interrupt source.
-      The value must be 2.
+    description: Specifies number of cells needed to encode an interrupt
+      source.
 
   interrupt-controller: true
 
   nvidia,invert-interrupt:
     $ref: /schemas/types.yaml#/definitions/flag
-    description: Inverts the PMU interrupt signal.
-      The PMU is an external Power Management Unit, whose interrupt output
-      signal is fed into the PMC. This signal is optionally inverted, and
-      then fed into the ARM GIC. The PMC is not involved in the detection
-      or handling of this interrupt signal, merely its inversion.
+    description: Inverts the PMU interrupt signal. The PMU is an external Power
+      Management Unit, whose interrupt output signal is fed into the PMC. This
+      signal is optionally inverted, and then fed into the ARM GIC. The PMC is
+      not involved in the detection or handling of this interrupt signal,
+      merely its inversion.
 
   nvidia,core-power-req-active-high:
     $ref: /schemas/types.yaml#/definitions/flag
-    description: Core power request active-high.
+    description: core power request active-high
 
   nvidia,sys-clock-req-active-high:
     $ref: /schemas/types.yaml#/definitions/flag
-    description: System clock request active-high.
+    description: system clock request active-high
 
   nvidia,combined-power-req:
     $ref: /schemas/types.yaml#/definitions/flag
-    description: combined power request for CPU and Core.
+    description: combined power request for CPU and core
 
   nvidia,cpu-pwr-good-en:
     $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      CPU power good signal from external PMIC to PMC is enabled.
+    description: CPU power good signal from external PMIC to PMC is enabled
 
   nvidia,suspend-mode:
     $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [0, 1, 2]
-    description:
-      The suspend mode that the platform should use.
-      Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
-      Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
-      Mode 2 is for LP2, CPU voltage off
+    description: the suspend mode that the platform should use
+    oneOf:
+      - description: LP0, CPU + Core voltage off and DRAM in self-refresh
+        const: 0
+      - description: LP1, CPU voltage off and DRAM in self-refresh
+        const: 1
+      - description: LP2, CPU voltage off
+        const: 2
 
   nvidia,cpu-pwr-good-time:
     $ref: /schemas/types.yaml#/definitions/uint32
-    description: CPU power good time in uSec.
+    description: CPU power good time in microseconds
 
   nvidia,cpu-pwr-off-time:
     $ref: /schemas/types.yaml#/definitions/uint32
-    description: CPU power off time in uSec.
+    description: CPU power off time in microseconds
 
   nvidia,core-pwr-good-time:
     $ref: /schemas/types.yaml#/definitions/uint32-array
-    description:
-      <Oscillator-stable-time Power-stable-time>
-      Core power good time in uSec.
+    description: core power good time in microseconds
+    items:
+      - description: oscillator stable time
+      - description: power stable time
 
   nvidia,core-pwr-off-time:
     $ref: /schemas/types.yaml#/definitions/uint32
-    description: Core power off time in uSec.
+    description: core power off time in microseconds
 
   nvidia,lp0-vec:
     $ref: /schemas/types.yaml#/definitions/uint32-array
-    description:
-      <start length> Starting address and length of LP0 vector.
-      The LP0 vector contains the warm boot code that is executed
-      by AVP when resuming from the LP0 state.
-      The AVP (Audio-Video Processor) is an ARM7 processor and
-      always being the first boot processor when chip is power on
-      or resume from deep sleep mode. When the system is resumed
-      from the deep sleep mode, the warm boot code will restore
-      some PLLs, clocks and then brings up CPU0 for resuming the
-      system.
+    description: |
+      Starting address and length of LP0 vector. The LP0 vector contains the
+      warm boot code that is executed by AVP when resuming from the LP0 state.
+      The AVP (Audio-Video Processor) is an ARM7 processor and always being
+      the first boot processor when chip is power on or resume from deep sleep
+      mode. When the system is resumed from the deep sleep mode, the warm boot
+      code will restore some PLLs, clocks and then brings up CPU0 for resuming
+      the system.
+    items:
+      - description: starting address of LP0 vector
+      - description: length of LP0 vector
 
   i2c-thermtrip:
     type: object
-    description:
-      On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
-      hardware-triggered thermal reset will be enabled.
+    description: On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode
+      exists, hardware-triggered thermal reset will be enabled.
 
     properties:
       nvidia,i2c-controller-id:
         $ref: /schemas/types.yaml#/definitions/uint32
-        description:
-          ID of I2C controller to send poweroff command to PMU.
-          Valid values are described in section 9.2.148
-          "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
-          Manual.
+        description: ID of I2C controller to send poweroff command to PMU.
+          Valid values are described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0"
+          of the Tegra K1 Technical Reference Manual.
 
       nvidia,bus-addr:
         $ref: /schemas/types.yaml#/definitions/uint32
-        description: Bus address of the PMU on the I2C bus.
+        description: bus address of the PMU on the I2C bus
 
       nvidia,reg-addr:
         $ref: /schemas/types.yaml#/definitions/uint32
-        description: PMU I2C register address to issue poweroff command.
+        description: PMU I2C register address to issue poweroff command
 
       nvidia,reg-data:
         $ref: /schemas/types.yaml#/definitions/uint32
-        description: Poweroff command to write to PMU.
+        description: power-off command to write to PMU
 
       nvidia,pinmux-id:
         $ref: /schemas/types.yaml#/definitions/uint32
-        description:
-          Pinmux used by the hardware when issuing Poweroff command.
-          Defaults to 0. Valid values are described in section 12.5.2
-          "Pinmux Support" of the Tegra4 Technical Reference Manual.
+        description: Pinmux used by the hardware when issuing power-off command.
+          Defaults to 0. Valid values are described in section 12.5.2 "Pinmux
+          Support" of the Tegra4 Technical Reference Manual.
 
     required:
       - nvidia,i2c-controller-id
@@ -165,65 +158,91 @@ properties:
 
     additionalProperties: false
 
+  core-domain:
+    type: object
+    description: The vast majority of hardware blocks of Tegra SoC belong to a
+      core power domain, which has a dedicated voltage rail that powers the
+      blocks.
+
+    properties:
+      operating-points-v2:
+        description: Should contain level, voltages and opp-supported-hw
+          property. The supported-hw is a bitfield indicating SoC speedo or
+          process ID mask.
+
+      "#power-domain-cells":
+        const: 0
+
+    required:
+      - operating-points-v2
+      - "#power-domain-cells"
+
+    additionalProperties: false
+
+  core-supply:
+    description: phandle to voltage regulator connected to the SoC core power
+      rail
+
   powergates:
     type: object
     description: |
-      This node contains a hierarchy of power domain nodes, which should
-      match the powergates on the Tegra SoC. Each powergate node
-      represents a power-domain on the Tegra SoC that can be power-gated
-      by the Tegra PMC.
-      Hardware blocks belonging to a power domain should contain
-      "power-domains" property that is a phandle pointing to corresponding
-      powergate node.
-      The name of the powergate node should be one of the below. Note that
-      not every powergate is applicable to all Tegra devices and the following
-      list shows which powergates are applicable to which devices.
-      Please refer to Tegra TRM for mode details on the powergate nodes to
-      use for each power-gate block inside Tegra.
-      Name		Description			            Devices Applicable
-      3d		  3D Graphics			            Tegra20/114/124/210
-      3d0		  3D Graphics 0		            Tegra30
-      3d1		  3D Graphics 1		            Tegra30
-      aud		  Audio				                Tegra210
-      dfd		  Debug				                Tegra210
-      dis		  Display A			              Tegra114/124/210
-      disb		Display B			              Tegra114/124/210
-      heg		  2D Graphics		            	Tegra30/114/124/210
-      iram		Internal RAM		            Tegra124/210
-      mpe		  MPEG Encode			            All
-      nvdec		NVIDIA Video Decode Engine	Tegra210
-      nvjpg		NVIDIA JPEG Engine		      Tegra210
-      pcie		PCIE				                Tegra20/30/124/210
-      sata		SATA				                Tegra30/124/210
-      sor		  Display interfaces       		Tegra124/210
-      ve2		  Video Encode Engine 2		    Tegra210
-      venc		Video Encode Engine		      All
-      vdec		Video Decode Engine		      Tegra20/30/114/124
-      vic		  Video Imaging Compositor	  Tegra124/210
-      xusba		USB Partition A			        Tegra114/124/210
-      xusbb		USB Partition B 		        Tegra114/124/210
-      xusbc		USB Partition C			        Tegra114/124/210
+      This node contains a hierarchy of power domain nodes, which should match
+      the powergates on the Tegra SoC. Each powergate node represents a power-
+      domain on the Tegra SoC that can be power-gated by the Tegra PMC.
+
+      Hardware blocks belonging to a power domain should contain "power-domains"
+      property that is a phandle pointing to corresponding powergate node.
+
+      The name of the powergate node should be one of the below. Note that not
+      every powergate is applicable to all Tegra devices and the following list
+      shows which powergates are applicable to which devices.
+
+      Please refer to Tegra TRM for mode details on the powergate nodes to use
+      for each power-gate block inside Tegra.
+
+        Name     Description                   Devices Applicable
+        --------------------------------------------------------------
+        3d       3D Graphics                   Tegra20/114/124/210
+        3d0      3D Graphics 0                 Tegra30
+        3d1      3D Graphics 1                 Tegra30
+        aud      Audio                         Tegra210
+        dfd      Debug                         Tegra210
+        dis      Display A                     Tegra114/124/210
+        disb     Display B                     Tegra114/124/210
+        heg      2D Graphics                   Tegra30/114/124/210
+        iram     Internal RAM                  Tegra124/210
+        mpe      MPEG Encode                   All
+        nvdec    NVIDIA Video Decode Engine    Tegra210
+        nvjpg    NVIDIA JPEG Engine            Tegra210
+        pcie     PCIE                          Tegra20/30/124/210
+        sata     SATA                          Tegra30/124/210
+        sor      Display interfaces            Tegra124/210
+        ve2      Video Encode Engine 2         Tegra210
+        venc     Video Encode Engine           All
+        vdec     Video Decode Engine           Tegra20/30/114/124
+        vic      Video Imaging Compositor      Tegra124/210
+        xusba    USB Partition A               Tegra114/124/210
+        xusbb    USB Partition B               Tegra114/124/210
+        xusbc    USB Partition C               Tegra114/124/210
 
     patternProperties:
       "^[a-z0-9]+$":
         type: object
-
-        patternProperties:
+        properties:
           clocks:
             minItems: 1
-            maxItems: 8
-            description:
-              Must contain an entry for each clock required by the PMC
-              for controlling a power-gate.
-              See ../clocks/clock-bindings.txt document for more details.
+            maxItems: 10
+            description: |
+              Must contain an entry for each clock required by the PMC for
+              controlling a powergate. See ../clocks/clock-bindings.txt document
+              for more details.
 
           resets:
             minItems: 1
             maxItems: 8
-            description:
-              Must contain an entry for each reset required by the PMC
-              for controlling a power-gate.
-              See ../reset/reset.txt for more details.
+            description: |
+              Must contain an entry for each reset required by the PMC for
+              controlling a powergate. See ../reset/reset.txt for more details.
 
           '#power-domain-cells':
             const: 0
@@ -236,96 +255,84 @@ properties:
 
     additionalProperties: false
 
-patternProperties:
-  "^[a-f0-9]+-[a-f0-9]+$":
+  pinmux:
     type: object
-    description:
-      This is a Pad configuration node. On Tegra SOCs a pad is a set of
-      pins which are configured as a group. The pin grouping is a fixed
-      attribute of the hardware. The PMC can be used to set pad power state
-      and signaling voltage. A pad can be either in active or power down mode.
-      The support for power state and signaling voltage configuration varies
-      depending on the pad in question. 3.3V and 1.8V signaling voltages
-      are supported on pins where software controllable signaling voltage
-      switching is available.
-
-      The pad configuration state nodes are placed under the pmc node and they
-      are referred to by the pinctrl client properties. For more information
-      see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
-      The pad name should be used as the value of the pins property in pin
-      configuration nodes.
-
-      The following pads are present on Tegra124 and Tegra132
-      audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic,
-      hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
-      sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias.
-
-      The following pads are present on Tegra210
-      audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
-      debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
-      hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
-      sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
-
     properties:
-      pins:
-        $ref: /schemas/types.yaml#/definitions/string
-        description: Must contain name of the pad(s) to be configured.
+      status: true
 
-      low-power-enable:
-        $ref: /schemas/types.yaml#/definitions/flag
-        description: Configure the pad into power down mode.
+    additionalProperties:
+      type: object
+      description: |
+        This is a pad configuration node. On Tegra SoCs a pad is a set of pins
+        which are configured as a group. The pin grouping is a fixed attribute
+        of the hardware. The PMC can be used to set pad power state and
+        signaling voltage. A pad can be either in active or power down mode.
+        The support for power state and signaling voltage configuration varies
+        depending on the pad in question. 3.3V and 1.8V signaling voltages are
+        supported on pins where software controllable signaling voltage
+        switching is available.
 
-      low-power-disable:
-        $ref: /schemas/types.yaml#/definitions/flag
-        description: Configure the pad into active mode.
+        The pad configuration state nodes are placed under the pmc node and
+        they are referred to by the pinctrl client properties. For more
+        information see:
 
-      power-source:
-        $ref: /schemas/types.yaml#/definitions/uint32
-        description:
-          Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
-          TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
-          The values are defined in
-          include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
-          Power state can be configured on all Tegra124 and Tegra132
-          pads. None of the Tegra124 or Tegra132 pads support signaling
-          voltage switching.
-          All of the listed Tegra210 pads except pex-cntrl support power
-          state configuration. Signaling voltage switching is supported
-          on below Tegra210 pads.
-          audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
-          sdmmc3, spi, spi-hv, and uart.
+          Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
 
-    required:
-      - pins
+        The pad name should be used as the value of the pins property in pin
+        configuration nodes.
 
-    additionalProperties: false
+        The following pads are present on Tegra124 and Tegra132:
 
-  core-domain:
-    type: object
-    description: |
-      The vast majority of hardware blocks of Tegra SoC belong to a
-      Core power domain, which has a dedicated voltage rail that powers
-      the blocks.
+          audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi,
+          hsic, hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2,
+          pex-cntrl, sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2,
+          usb_bias
 
-    properties:
-      operating-points-v2:
-        description:
-          Should contain level, voltages and opp-supported-hw property.
-          The supported-hw is a bitfield indicating SoC speedo or process
-          ID mask.
+        The following pads are present on Tegra210:
 
-      "#power-domain-cells":
-        const: 0
+          audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
+          debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio,
+          hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
+          sdmmc1, sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias
 
-    required:
-      - operating-points-v2
-      - "#power-domain-cells"
+      properties:
+        pins:
+          $ref: /schemas/types.yaml#/definitions/string-array
+          description: Must contain name of the pad(s) to be configured.
 
-    additionalProperties: false
+        low-power-enable:
+          $ref: /schemas/types.yaml#/definitions/flag
+          description: Configure the pad into power down mode.
 
-  core-supply:
-    description:
-      Phandle to voltage regulator connected to the SoC Core power rail.
+        low-power-disable:
+          $ref: /schemas/types.yaml#/definitions/flag
+          description: Configure the pad into active mode.
+
+        power-source:
+          $ref: /schemas/types.yaml#/definitions/uint32
+          description: |
+            Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
+            TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. The
+            values are defined in:
+
+              include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
+
+            Power state can be configured on all Tegra124 and Tegra132 pads.
+            None of the Tegra124 or Tegra132 pads support signaling voltage
+            switching. All of the listed Tegra210 pads except pex-cntrl support
+            power state configuration. Signaling voltage switching is supported
+            on the following Tegra210 pads:
+
+              audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, sdmmc3,
+              spi, spi-hv, uart
+
+        phandle:
+          $ref: /schemas/types.yaml#/definitions/uint32
+
+      required:
+        - pins
+
+      additionalProperties: false
 
 required:
   - compatible
@@ -334,6 +341,52 @@ required:
   - clocks
   - '#clock-cells'
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra124-pmc
+    then:
+      properties:
+        pinmux:
+          properties:
+            status: true
+
+          additionalProperties:
+            type: object
+            properties:
+              pins:
+                items:
+                  enum: [ audio, bb, cam, comp, csia, csb, cse, dsi, dsib,
+                          dsic, dsid, hdmi, hsic, hv, lvds, mipi-bias, nand,
+                          pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
+                          sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2,
+                          usb_bias ]
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra210-pmc
+    then:
+      properties:
+        pinmux:
+          properties:
+            status: true
+
+          additionalProperties:
+            type: object
+            properties:
+              pins:
+                items:
+                  enum: [ audio, audio-hv, cam, csia, csib, csic, csid, csie,
+                          csif, dbg, debug-nonao, dmic, dp, dsi, dsib, dsic,
+                          dsid, emmc, emmc2, gpio, hdmi, hsic, lvds, mipi-bias,
+                          pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
+                          sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3,
+                          usb-bias ]
+
 additionalProperties: false
 
 dependencies:
@@ -343,47 +396,46 @@ dependencies:
 
 examples:
   - |
-
     #include <dt-bindings/clock/tegra210-car.h>
     #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
     #include <dt-bindings/soc/tegra-pmc.h>
 
-    tegra_pmc: pmc@7000e400 {
-              compatible = "nvidia,tegra210-pmc";
-              reg = <0x7000e400 0x400>;
-              core-supply = <&regulator>;
-              clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
-              clock-names = "pclk", "clk32k_in";
-              #clock-cells = <1>;
-
-              nvidia,invert-interrupt;
-              nvidia,suspend-mode = <0>;
-              nvidia,cpu-pwr-good-time = <0>;
-              nvidia,cpu-pwr-off-time = <0>;
-              nvidia,core-pwr-good-time = <4587 3876>;
-              nvidia,core-pwr-off-time = <39065>;
-              nvidia,core-power-req-active-high;
-              nvidia,sys-clock-req-active-high;
-
-              pd_core: core-domain {
-                      operating-points-v2 = <&core_opp_table>;
-                      #power-domain-cells = <0>;
-              };
-
-              powergates {
-                    pd_audio: aud {
-                            clocks = <&tegra_car TEGRA210_CLK_APE>,
-                                     <&tegra_car TEGRA210_CLK_APB2APE>;
-                            resets = <&tegra_car 198>;
-                            power-domains = <&pd_core>;
-                            #power-domain-cells = <0>;
-                    };
-
-                    pd_xusbss: xusba {
-                            clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
-                            resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
-                            power-domains = <&pd_core>;
-                            #power-domain-cells = <0>;
-                    };
-              };
+    pmc@7000e400 {
+      compatible = "nvidia,tegra210-pmc";
+      reg = <0x7000e400 0x400>;
+      core-supply = <&regulator>;
+      clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
+      clock-names = "pclk", "clk32k_in";
+      #clock-cells = <1>;
+
+      nvidia,invert-interrupt;
+      nvidia,suspend-mode = <0>;
+      nvidia,cpu-pwr-good-time = <0>;
+      nvidia,cpu-pwr-off-time = <0>;
+      nvidia,core-pwr-good-time = <4587 3876>;
+      nvidia,core-pwr-off-time = <39065>;
+      nvidia,core-power-req-active-high;
+      nvidia,sys-clock-req-active-high;
+
+      pd_core: core-domain {
+        operating-points-v2 = <&core_opp_table>;
+        #power-domain-cells = <0>;
+      };
+
+      powergates {
+        pd_audio: aud {
+          clocks = <&tegra_car TEGRA210_CLK_APE>,
+                   <&tegra_car TEGRA210_CLK_APB2APE>;
+          resets = <&tegra_car 198>;
+          power-domains = <&pd_core>;
+          #power-domain-cells = <0>;
+        };
+
+        pd_xusbss: xusba {
+          clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
+          resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
+          power-domains = <&pd_core>;
+          #power-domain-cells = <0>;
+        };
+      };
     };
-- 
2.36.1

[PATCH 5/5] dt-bindings: arm: tegra: Add missing compatible strings

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The Nyan Blaze and Nyan Big, as well as Jetson Nano (P3450-0000), Darcy
(P2894-0050-A08) and Pixel C (Smaug) were never mentioned. Add them.

While at it, also fix a typo in the compatible string for Apalis Tegra30
v1.1 evaluation board.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../devicetree/bindings/arm/tegra.yaml        | 50 ++++++++++++++++++-
 1 file changed, 48 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml
index 49841ca272ee..187d832a14ac 100644
--- a/Documentation/devicetree/bindings/arm/tegra.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra.yaml
@@ -114,6 +114,33 @@ properties:
           - const: toradex,apalis-tk1-v1.2
           - const: toradex,apalis-tk1
           - const: nvidia,tegra124
+      - items:
+          - const: google,nyan-big-rev7
+          - const: google,nyan-big-rev6
+          - const: google,nyan-big-rev5
+          - const: google,nyan-big-rev4
+          - const: google,nyan-big-rev3
+          - const: google,nyan-big-rev2
+          - const: google,nyan-big-rev1
+          - const: google,nyan-big-rev0
+          - const: google,nyan-big
+          - const: google,nyan
+          - const: nvidia,tegra124
+      - items:
+          - const: google,nyan-blaze-rev10
+          - const: google,nyan-blaze-rev9
+          - const: google,nyan-blaze-rev8
+          - const: google,nyan-blaze-rev7
+          - const: google,nyan-blaze-rev6
+          - const: google,nyan-blaze-rev5
+          - const: google,nyan-blaze-rev4
+          - const: google,nyan-blaze-rev3
+          - const: google,nyan-blaze-rev2
+          - const: google,nyan-blaze-rev1
+          - const: google,nyan-blaze-rev0
+          - const: google,nyan-blaze
+          - const: google,nyan
+          - const: nvidia,tegra124
       - items:
           - enum:
               - nvidia,norrin
@@ -121,11 +148,30 @@ properties:
           - const: nvidia,tegra124
       - items:
           - enum:
-              - nvidia,darcy
               - nvidia,p2371-0000
               - nvidia,p2371-2180
               - nvidia,p2571
-              - nvidia,p2894-0050-a08
+          - const: nvidia,tegra210
+      - description: NVIDIA Jetson Nano
+        items:
+          - const: nvidia,p3450-0000
+          - const: nvidia,tegra210
+      - description: NVIDIA Shield TV
+        items:
+          - const: nvidia,p2894-0050-a08
+          - const: nvidia,darcy
+          - const: nvidia,tegra210
+      - description: Google Pixel C
+        items:
+          - const: google,smaug-rev8
+          - const: google,smaug-rev7
+          - const: google,smaug-rev6
+          - const: google,smaug-rev5
+          - const: google,smaug-rev4
+          - const: google,smaug-rev3
+          - const: google,smaug-rev2
+          - const: google,smaug-rev1
+          - const: google,smaug
           - const: nvidia,tegra210
       - description: Jetson TX2 Developer Kit
         items:
-- 
2.36.1

Re: [PATCH 5/5] dt-bindings: arm: tegra: Add missing compatible strings

[Francesco Dolcini]

Hello Thierry

On Mon, Jul 11, 2022 at 05:20:20PM +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> While at it, also fix a typo in the compatible string for Apalis Tegra30
> v1.1 evaluation board.

Appreciated! Maybe you can double check the Apalis change? I cannot see any
related change in the patch.

Francesco

Re: [PATCH 5/5] dt-bindings: arm: tegra: Add missing compatible strings

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1196 bytes --]

On Mon, Jul 11, 2022 at 05:36:43PM +0200, Francesco Dolcini wrote:
> Hello Thierry
> 
> On Mon, Jul 11, 2022 at 05:20:20PM +0200, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > While at it, also fix a typo in the compatible string for Apalis Tegra30
> > v1.1 evaluation board.
> 
> Appreciated! Maybe you can double check the Apalis change? I cannot see any
> related change in the patch.

Heh... looks like this was already fixed by David almost a year ago:

	commit 55c21d57eafb7b379bb7b3e93baf9ca2695895b0
	Author: David Heidelberg <david@ixit.cz>
	Date:   Sun Sep 12 18:51:20 2021 +0200

	    dt-bindings: arm: Fix Toradex compatible typo
	    
	    Fix board compatible typo reported by dtbs_check.
	    
	    Fixes: f4d1577e9bc6 ("dt-bindings: arm: Convert Tegra board/soc bindings to json-schema")
	    Signed-off-by: David Heidelberg <david@ixit.cz>
	    Link: https://lore.kernel.org/r/20210912165120.188490-1-david@ixit.cz
	    Signed-off-by: Rob Herring <robh@kernel.org>

Clearly I have been carrying these patches locally for way too long...

Thanks for noticing, I'll drop that comment from the commit message.

Thierry

[-- Attachment #2: signature.asc --]
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Re: [PATCH 1/5] dt-bindings: arm: tegra: flowctrl: Convert to json-schema

[Krzysztof Kozlowski]

On 11/07/2022 17:20, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Convert the Tegra flow controller bindings from the free-form text
> format to json-schema.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../arm/tegra/nvidia,tegra20-flowctrl.txt     | 18 --------
>  .../arm/tegra/nvidia,tegra20-flowctrl.yaml    | 41 +++++++++++++++++++

arm directory is for top-level stuff only. SoC components which do not
fit any subsustem, should go to "soc". Can you move it here to "soc" or
to respective subsystem (net?) if there is such?

Rest looks good, so with different directory:

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH 2/5] dt-bindings: arm: tegra: ahb: Convert to json-schema

[Krzysztof Kozlowski]

On 11/07/2022 17:20, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Convert the NVIDIA Tegra AHB bindings from the free-form text format to
> json-schema.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../bindings/arm/tegra/nvidia,tegra20-ahb.txt | 17 --------
>  .../arm/tegra/nvidia,tegra20-ahb.yaml         | 39 +++++++++++++++++++
>  2 files changed, 39 insertions(+), 17 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt
>  create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.yaml
> 
> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt
> deleted file mode 100644
> index 9a4295b54539..000000000000
> --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt
> +++ /dev/null
> @@ -1,17 +0,0 @@
> -NVIDIA Tegra AHB
> -
> -Required properties:
> -- compatible : For Tegra20, must contain "nvidia,tegra20-ahb".  For
> -  Tegra30, must contain "nvidia,tegra30-ahb".  Otherwise, must contain
> -  '"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,
> -  tegra132, or tegra210.
> -- reg : Should contain 1 register ranges(address and length).  For
> -  Tegra20, Tegra30, and Tegra114 chips, the value must be <0x6000c004
> -  0x10c>.  For Tegra124, Tegra132 and Tegra210 chips, the value should
> -  be be <0x6000c000 0x150>.
> -
> -Example (for a Tegra20 chip):
> -	ahb: ahb@6000c004 {
> -		compatible = "nvidia,tegra20-ahb";
> -		reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
> -	};
> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.yaml
> new file mode 100644
> index 000000000000..6d9baab76258
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.yaml

Same comment as for #1 - move to "soc", please.

> @@ -0,0 +1,39 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-ahb.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +maintainers:
> +  - Thierry Reding <thierry.reding@gmail.com>
> +  - Jon Hunter <jonathanh@nvidia.com>
> +
> +title: NVIDIA Tegra AHB
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - const: nvidia,tegra20-ahb
> +      - const: nvidia,tegra30-ahb

These two should be an enum.

> +      - items:
> +          - enum:
> +              - nvidia,tegra114-ahb
> +              - nvidia,tegra124-ahb
> +              - nvidia,tegra210-ahb
> +          - const: nvidia,tegra30-ahb
> +
> +  reg:
> +    maxItems: 1
> +
> +additionalProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +
> +examples:
> +  - |
> +    ahb@6000c004 {
> +      compatible = "nvidia,tegra20-ahb";
> +      reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
> +    };

In your first patch, you used 4-spaces indentation (preferred) for DTS
example. How about using 4-space also here?


Best regards,
Krzysztof

Re: [PATCH 3/5] dt-bindings: arm: tegra: nvec: Convert to json-schema

[Krzysztof Kozlowski]

On 11/07/2022 17:20, Thierry Reding wrote:
> +---
> +$id: http://devicetree.org/schemas/arm/tegra/nvidia,nvec.yaml#

Same comment -> under soc.

> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA compliant embedded controller
> +
> +maintainers:
> +  - Thierry Reding <thierry.reding@gmail.com>
> +  - Jon Hunter <jonathanh@nvidia.com>
> +
> +properties:
> +  compatible:
> +    const: nvidia,nvec
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    minItems: 1
> +    items:
> +      - description: divider clock
> +      - description: fast clock
> +
> +  clock-names:
> +    minItems: 1
> +    items:
> +      - const: div-clk
> +      - const: fast-clk
> +
> +  resets:
> +    items:
> +      - description: module reset
> +
> +  reset-names:
> +    items:
> +      - const: i2c
> +
> +  clock-frequency:
> +    $ref: /schemas/types.yaml#/definitions/uint32

No need for ref, standard property (from core schema).

> +    description: frequency of the I2C bus
> +
> +  request-gpios:


Best regards,
Krzysztof

Re: [PATCH 4/5] dt-bindings: arm: tegra: Revise Tegra20 PMC bindings

[Krzysztof Kozlowski]

On 11/07/2022 17:20, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Update the Tegra20 PMC bindings to make use of some advanced json-schema
> features such as describing list elements or validating the contents of
> string arrays.
> 
> While at it, also restructure the pad configuration node schema to make
> sure it doesn't accidentally match other properties.

Please split cosmetic changes like these around descriptions, from
functional ones.

The patch is also too big to review - I have no clue if some changes are
just for description or you move/change entire properties (like
core-domain, pinmux).

> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../arm/tegra/nvidia,tegra20-pmc.yaml         | 512 ++++++++++--------
>  1 file changed, 282 insertions(+), 230 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> index 564ae6aaccf7..6894addb3c9a 100644
> --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> @@ -1,4 +1,4 @@
> -# SPDX-License-Identifier: GPL-2.0
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>  %YAML 1.2
>  ---
>  $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
> @@ -21,141 +21,134 @@ properties:
>  
>    reg:
>      maxItems: 1
> -    description:
> -      Offset and length of the register set for the device.
> +    description: Offset and length of the register set for the device.
>  
>    clock-names:
>      items:
>        - const: pclk
>        - const: clk32k_in
> -    description:
> -      Must includes entries pclk and clk32k_in.
> -      pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
> -      input to Tegra.
> +    description: Must includes entries pclk and clk32k_in. pclk is the Tegra
> +      clock of that name and clk32k_in is 32KHz clock input to Tegra.
>  
>    clocks:
>      maxItems: 2
> -    description:
> -      Must contain an entry for each entry in clock-names.
> -      See ../clocks/clocks-bindings.txt for details.
> +    description: Must contain an entry for each entry in clock-names. See
> +      ../clocks/clocks-bindings.txt for details.

Drop entire description instead. It's useless in context of DT schema.

>  
>    '#clock-cells':
>      const: 1
> -    description:
> -      Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
> -      PMC also has blink control which allows 32Khz clock output to
> -      Tegra blink pad.
> -      Consumer of PMC clock should specify the desired clock by having
> -      the clock ID in its "clocks" phandle cell with pmc clock provider.
> -      See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
> -      clock IDs.
> +    description: |
> +      Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. PMC also has blink
> +      control which allows 32Khz clock output to Tegra blink pad.
> +
> +      Consumer of PMC clock should specify the desired clock by having the
> +      clock ID in its "clocks" phandle cell with PMC clock provider. See
> +      include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC clock IDs.
>  
>    '#interrupt-cells':
>      const: 2
> -    description:
> -      Specifies number of cells needed to encode an interrupt source.
> -      The value must be 2.
> +    description: Specifies number of cells needed to encode an interrupt
> +      source.
>  
>    interrupt-controller: true
>  
>    nvidia,invert-interrupt:
>      $ref: /schemas/types.yaml#/definitions/flag
> -    description: Inverts the PMU interrupt signal.
> -      The PMU is an external Power Management Unit, whose interrupt output
> -      signal is fed into the PMC. This signal is optionally inverted, and
> -      then fed into the ARM GIC. The PMC is not involved in the detection
> -      or handling of this interrupt signal, merely its inversion.
> +    description: Inverts the PMU interrupt signal. The PMU is an external Power
> +      Management Unit, whose interrupt output signal is fed into the PMC. This
> +      signal is optionally inverted, and then fed into the ARM GIC. The PMC is
> +      not involved in the detection or handling of this interrupt signal,
> +      merely its inversion.
>  
>    nvidia,core-power-req-active-high:
>      $ref: /schemas/types.yaml#/definitions/flag
> -    description: Core power request active-high.
> +    description: core power request active-high
>  
>    nvidia,sys-clock-req-active-high:
>      $ref: /schemas/types.yaml#/definitions/flag
> -    description: System clock request active-high.
> +    description: system clock request active-high
>  
>    nvidia,combined-power-req:
>      $ref: /schemas/types.yaml#/definitions/flag
> -    description: combined power request for CPU and Core.
> +    description: combined power request for CPU and core
>  
>    nvidia,cpu-pwr-good-en:
>      $ref: /schemas/types.yaml#/definitions/flag
> -    description:
> -      CPU power good signal from external PMIC to PMC is enabled.
> +    description: CPU power good signal from external PMIC to PMC is enabled
>  
>    nvidia,suspend-mode:
>      $ref: /schemas/types.yaml#/definitions/uint32
> -    enum: [0, 1, 2]
> -    description:
> -      The suspend mode that the platform should use.
> -      Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
> -      Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
> -      Mode 2 is for LP2, CPU voltage off
> +    description: the suspend mode that the platform should use
> +    oneOf:
> +      - description: LP0, CPU + Core voltage off and DRAM in self-refresh
> +        const: 0
> +      - description: LP1, CPU voltage off and DRAM in self-refresh
> +        const: 1
> +      - description: LP2, CPU voltage off
> +        const: 2
>  
>    nvidia,cpu-pwr-good-time:
>      $ref: /schemas/types.yaml#/definitions/uint32
> -    description: CPU power good time in uSec.
> +    description: CPU power good time in microseconds
>  
>    nvidia,cpu-pwr-off-time:
>      $ref: /schemas/types.yaml#/definitions/uint32
> -    description: CPU power off time in uSec.
> +    description: CPU power off time in microseconds
>  
>    nvidia,core-pwr-good-time:
>      $ref: /schemas/types.yaml#/definitions/uint32-array
> -    description:
> -      <Oscillator-stable-time Power-stable-time>
> -      Core power good time in uSec.
> +    description: core power good time in microseconds
> +    items:
> +      - description: oscillator stable time
> +      - description: power stable time
>  
>    nvidia,core-pwr-off-time:
>      $ref: /schemas/types.yaml#/definitions/uint32
> -    description: Core power off time in uSec.
> +    description: core power off time in microseconds
>  
>    nvidia,lp0-vec:
>      $ref: /schemas/types.yaml#/definitions/uint32-array
> -    description:
> -      <start length> Starting address and length of LP0 vector.
> -      The LP0 vector contains the warm boot code that is executed
> -      by AVP when resuming from the LP0 state.
> -      The AVP (Audio-Video Processor) is an ARM7 processor and
> -      always being the first boot processor when chip is power on
> -      or resume from deep sleep mode. When the system is resumed
> -      from the deep sleep mode, the warm boot code will restore
> -      some PLLs, clocks and then brings up CPU0 for resuming the
> -      system.
> +    description: |
> +      Starting address and length of LP0 vector. The LP0 vector contains the
> +      warm boot code that is executed by AVP when resuming from the LP0 state.
> +      The AVP (Audio-Video Processor) is an ARM7 processor and always being
> +      the first boot processor when chip is power on or resume from deep sleep
> +      mode. When the system is resumed from the deep sleep mode, the warm boot
> +      code will restore some PLLs, clocks and then brings up CPU0 for resuming
> +      the system.
> +    items:
> +      - description: starting address of LP0 vector
> +      - description: length of LP0 vector
>  
>    i2c-thermtrip:
>      type: object
> -    description:
> -      On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
> -      hardware-triggered thermal reset will be enabled.
> +    description: On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode
> +      exists, hardware-triggered thermal reset will be enabled.
>  
>      properties:
>        nvidia,i2c-controller-id:
>          $ref: /schemas/types.yaml#/definitions/uint32
> -        description:
> -          ID of I2C controller to send poweroff command to PMU.
> -          Valid values are described in section 9.2.148
> -          "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
> -          Manual.
> +        description: ID of I2C controller to send poweroff command to PMU.
> +          Valid values are described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0"
> +          of the Tegra K1 Technical Reference Manual.
>  
>        nvidia,bus-addr:
>          $ref: /schemas/types.yaml#/definitions/uint32
> -        description: Bus address of the PMU on the I2C bus.
> +        description: bus address of the PMU on the I2C bus
>  
>        nvidia,reg-addr:
>          $ref: /schemas/types.yaml#/definitions/uint32
> -        description: PMU I2C register address to issue poweroff command.
> +        description: PMU I2C register address to issue poweroff command
>  
>        nvidia,reg-data:
>          $ref: /schemas/types.yaml#/definitions/uint32
> -        description: Poweroff command to write to PMU.
> +        description: power-off command to write to PMU
>  
>        nvidia,pinmux-id:
>          $ref: /schemas/types.yaml#/definitions/uint32
> -        description:
> -          Pinmux used by the hardware when issuing Poweroff command.
> -          Defaults to 0. Valid values are described in section 12.5.2
> -          "Pinmux Support" of the Tegra4 Technical Reference Manual.
> +        description: Pinmux used by the hardware when issuing power-off command.
> +          Defaults to 0. Valid values are described in section 12.5.2 "Pinmux
> +          Support" of the Tegra4 Technical Reference Manual.
>  
>      required:
>        - nvidia,i2c-controller-id
> @@ -165,65 +158,91 @@ properties:
>  
>      additionalProperties: false
>  
> +  core-domain:
> +    type: object
> +    description: The vast majority of hardware blocks of Tegra SoC belong to a
> +      core power domain, which has a dedicated voltage rail that powers the
> +      blocks.
> +
> +    properties:
> +      operating-points-v2:
> +        description: Should contain level, voltages and opp-supported-hw
> +          property. The supported-hw is a bitfield indicating SoC speedo or
> +          process ID mask.
> +
> +      "#power-domain-cells":
> +        const: 0
> +
> +    required:
> +      - operating-points-v2
> +      - "#power-domain-cells"
> +
> +    additionalProperties: false
> +
> +  core-supply:
> +    description: phandle to voltage regulator connected to the SoC core power
> +      rail

(...)

>  
>  required:
>    - compatible
> @@ -334,6 +341,52 @@ required:
>    - clocks
>    - '#clock-cells'
>  
> +allOf:
> +  - if:
> +      properties:

This is entirely new stuff. Don't mix with some cleanups.

> +        compatible:
> +          contains:
> +            const: nvidia,tegra124-pmc
> +    then:
> +      properties:
> +        pinmux:
> +          properties:
> +            status: true
> +
> +          additionalProperties:
> +            type: object
> +            properties:
> +              pins:
> +                items:
> +                  enum: [ audio, bb, cam, comp, csia, csb, cse, dsi, dsib,
> +                          dsic, dsid, hdmi, hsic, hv, lvds, mipi-bias, nand,
> +                          pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
> +                          sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2,
> +                          usb_bias ]
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: nvidia,tegra210-pmc
> +    then:
> +      properties:
> +        pinmux:
> +          properties:
> +            status: true
> +
> +          additionalProperties:
> +            type: object
> +            properties:
> +              pins:
> +                items:
> +                  enum: [ audio, audio-hv, cam, csia, csib, csic, csid, csie,
> +                          csif, dbg, debug-nonao, dmic, dp, dsi, dsib, dsic,
> +                          dsid, emmc, emmc2, gpio, hdmi, hsic, lvds, mipi-bias,
> +                          pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
> +                          sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3,
> +                          usb-bias ]
> +
>  additionalProperties: false


Best regards,
Krzysztof

Re: [PATCH 5/5] dt-bindings: arm: tegra: Add missing compatible strings

[Krzysztof Kozlowski]

On 11/07/2022 17:20, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The Nyan Blaze and Nyan Big, as well as Jetson Nano (P3450-0000), Darcy
> (P2894-0050-A08) and Pixel C (Smaug) were never mentioned. Add them.
> 
> While at it, also fix a typo in the compatible string for Apalis Tegra30
> v1.1 evaluation board.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>



Best regards,
Krzysztof

Re: [PATCH 3/5] dt-bindings: arm: tegra: nvec: Convert to json-schema

[Marc Dietrich]

Hello Thierry,

On Mon, 11 Jul 2022, Thierry Reding wrote:

> From: Thierry Reding <treding@nvidia.com>
>
> Convert the NVIDIA embedded controller bindings from the free-form text
> format to json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Marc,
>
> you authored this binding a long time ago, which makes the default
> license for this GPL-2.0. However, the preference is for DT bindings to
> be dual-licensed under the more permissive GPL-2.0-only OR BSD-2-Clause
> as done in this patch. Do you have any objections to relicensing?

yeah, that was almost 11 years ago - how fast time can pass ...
I'm ok with relicensing (and also for the conversion to yaml) - thanks for
taking care!

Acked-by: Marc Dietrich <marvin24@gmx.de>

Marc


> Thierry
>
> .../bindings/arm/tegra/nvidia,nvec.txt        | 21 -----
> .../bindings/arm/tegra/nvidia,nvec.yaml       | 94 +++++++++++++++++++
> 2 files changed, 94 insertions(+), 21 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt
> create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.yaml>
....