* [PATCH v4 1/9] dt-bindings: power: Add Tegra234 MGBE power domains
2022-07-07 7:48 [PATCH v4 0/9] tegra: Add support for MGBE controller Thierry Reding
@ 2022-07-07 7:48 ` Thierry Reding
2022-07-07 7:48 ` [PATCH v4 2/9] dt-bindings: Add Tegra234 MGBE clocks and resets Thierry Reding
` (7 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Thierry Reding @ 2022-07-07 7:48 UTC (permalink / raw)
To: Thierry Reding
Cc: Jon Hunter, Rob Herring, Krzysztof Kozlowski, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Bhadram Varka,
devicetree, linux-tegra, netdev, Krzysztof Kozlowski
From: Thierry Reding <treding@nvidia.com>
Add power domain IDs for the four Multi-Gigabit Ethernet (MGBE) power
partitions found on NVIDIA Tegra234.
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
include/dt-bindings/power/tegra234-powergate.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h
index f610eee9bce8..df1d4dd8dcf3 100644
--- a/include/dt-bindings/power/tegra234-powergate.h
+++ b/include/dt-bindings/power/tegra234-powergate.h
@@ -18,5 +18,6 @@
#define TEGRA234_POWER_DOMAIN_MGBEA 17U
#define TEGRA234_POWER_DOMAIN_MGBEB 18U
#define TEGRA234_POWER_DOMAIN_MGBEC 19U
+#define TEGRA234_POWER_DOMAIN_MGBED 20U
#endif
--
2.36.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 2/9] dt-bindings: Add Tegra234 MGBE clocks and resets
2022-07-07 7:48 [PATCH v4 0/9] tegra: Add support for MGBE controller Thierry Reding
2022-07-07 7:48 ` [PATCH v4 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Thierry Reding
@ 2022-07-07 7:48 ` Thierry Reding
2022-07-07 7:48 ` [PATCH v4 3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients Thierry Reding
` (6 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Thierry Reding @ 2022-07-07 7:48 UTC (permalink / raw)
To: Thierry Reding
Cc: Jon Hunter, Rob Herring, Krzysztof Kozlowski, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Bhadram Varka,
devicetree, linux-tegra, netdev, Krzysztof Kozlowski
From: Thierry Reding <treding@nvidia.com>
Add the clocks and resets used by the Multi-Gigabit Ethernet (MGBE)
hardware found on NVIDIA Tegra234 SoCs.
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
include/dt-bindings/clock/tegra234-clock.h | 101 +++++++++++++++++++++
include/dt-bindings/reset/tegra234-reset.h | 8 ++
2 files changed, 109 insertions(+)
diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
index bd4c3086a2da..bab85d9ba8cd 100644
--- a/include/dt-bindings/clock/tegra234-clock.h
+++ b/include/dt-bindings/clock/tegra234-clock.h
@@ -164,10 +164,111 @@
#define TEGRA234_CLK_PEX1_C5_CORE 225U
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
#define TEGRA234_CLK_PLLC4 237U
+/** @brief RX clock recovered from MGBE0 lane input */
+#define TEGRA234_CLK_MGBE0_RX_INPUT 248U
+/** @brief RX clock recovered from MGBE1 lane input */
+#define TEGRA234_CLK_MGBE1_RX_INPUT 249U
+/** @brief RX clock recovered from MGBE2 lane input */
+#define TEGRA234_CLK_MGBE2_RX_INPUT 250U
+/** @brief RX clock recovered from MGBE3 lane input */
+#define TEGRA234_CLK_MGBE3_RX_INPUT 251U
/** @brief 32K input clock provided by PMIC */
#define TEGRA234_CLK_CLK_32K 289U
+/** @brief Monitored branch of MBGE0 RX input clock */
+#define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U
+/** @brief Monitored branch of MBGE1 RX input clock */
+#define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U
+/** @brief Monitored branch of MBGE2 RX input clock */
+#define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U
+/** @brief Monitored branch of MBGE3 RX input clock */
+#define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U
+/** @brief Monitored branch of MGBE0 RX PCS mux output */
+#define TEGRA234_CLK_MGBE0_RX_PCS_M 361U
+/** @brief Monitored branch of MGBE1 RX PCS mux output */
+#define TEGRA234_CLK_MGBE1_RX_PCS_M 362U
+/** @brief Monitored branch of MGBE2 RX PCS mux output */
+#define TEGRA234_CLK_MGBE2_RX_PCS_M 363U
+/** @brief Monitored branch of MGBE3 RX PCS mux output */
+#define TEGRA234_CLK_MGBE3_RX_PCS_M 364U
+/** @brief RX PCS clock recovered from MGBE0 lane input */
+#define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U
+/** @brief RX PCS clock recovered from MGBE1 lane input */
+#define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U
+/** @brief RX PCS clock recovered from MGBE2 lane input */
+#define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U
+/** @brief RX PCS clock recovered from MGBE3 lane input */
+#define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U
+/** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */
+#define TEGRA234_CLK_MGBE0_RX_PCS 373U
+/** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */
+#define TEGRA234_CLK_MGBE0_TX 374U
+/** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */
+#define TEGRA234_CLK_MGBE0_TX_PCS 375U
+/** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */
+#define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U
+/** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */
+#define TEGRA234_CLK_MGBE0_MAC 377U
+/** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */
+#define TEGRA234_CLK_MGBE0_MACSEC 378U
+/** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */
+#define TEGRA234_CLK_MGBE0_EEE_PCS 379U
+/** @brief GBE_UPHY_MGBE0_APP_CLK gate output */
+#define TEGRA234_CLK_MGBE0_APP 380U
+/** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */
+#define TEGRA234_CLK_MGBE0_PTP_REF 381U
+/** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */
+#define TEGRA234_CLK_MGBE1_RX_PCS 382U
+/** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */
+#define TEGRA234_CLK_MGBE1_TX 383U
+/** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */
+#define TEGRA234_CLK_MGBE1_TX_PCS 384U
+/** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */
+#define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U
+/** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */
+#define TEGRA234_CLK_MGBE1_MAC 386U
+/** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */
+#define TEGRA234_CLK_MGBE1_EEE_PCS 388U
+/** @brief GBE_UPHY_MGBE1_APP_CLK gate output */
+#define TEGRA234_CLK_MGBE1_APP 389U
+/** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */
+#define TEGRA234_CLK_MGBE1_PTP_REF 390U
+/** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */
+#define TEGRA234_CLK_MGBE2_RX_PCS 391U
+/** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */
+#define TEGRA234_CLK_MGBE2_TX 392U
+/** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */
+#define TEGRA234_CLK_MGBE2_TX_PCS 393U
+/** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */
+#define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U
+/** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */
+#define TEGRA234_CLK_MGBE2_MAC 395U
+/** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */
+#define TEGRA234_CLK_MGBE2_EEE_PCS 397U
+/** @brief GBE_UPHY_MGBE2_APP_CLK gate output */
+#define TEGRA234_CLK_MGBE2_APP 398U
+/** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */
+#define TEGRA234_CLK_MGBE2_PTP_REF 399U
+/** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */
+#define TEGRA234_CLK_MGBE3_RX_PCS 400U
+/** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */
+#define TEGRA234_CLK_MGBE3_TX 401U
+/** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */
+#define TEGRA234_CLK_MGBE3_TX_PCS 402U
+/** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */
+#define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U
+/** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */
+#define TEGRA234_CLK_MGBE3_MAC 404U
+/** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */
+#define TEGRA234_CLK_MGBE3_MACSEC 405U
+/** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */
+#define TEGRA234_CLK_MGBE3_EEE_PCS 406U
+/** @brief GBE_UPHY_MGBE3_APP_CLK gate output */
+#define TEGRA234_CLK_MGBE3_APP 407U
+/** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */
+#define TEGRA234_CLK_MGBE3_PTP_REF 408U
/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */
#define TEGRA234_CLK_AZA_2XBIT 457U
/** @brief aza_2xbitclk / 2 (aza_bitclk) */
#define TEGRA234_CLK_AZA_BIT 458U
+
#endif
diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h
index 547ca3b60caa..55e397823a38 100644
--- a/include/dt-bindings/reset/tegra234-reset.h
+++ b/include/dt-bindings/reset/tegra234-reset.h
@@ -29,6 +29,12 @@
#define TEGRA234_RESET_I2C7 33U
#define TEGRA234_RESET_I2C8 34U
#define TEGRA234_RESET_I2C9 35U
+#define TEGRA234_RESET_MGBE0_PCS 45U
+#define TEGRA234_RESET_MGBE0_MAC 46U
+#define TEGRA234_RESET_MGBE1_PCS 49U
+#define TEGRA234_RESET_MGBE1_MAC 50U
+#define TEGRA234_RESET_MGBE2_PCS 53U
+#define TEGRA234_RESET_MGBE2_MAC 54U
#define TEGRA234_RESET_PEX2_CORE_10 56U
#define TEGRA234_RESET_PEX2_CORE_10_APB 57U
#define TEGRA234_RESET_PEX2_COMMON_APB 58U
@@ -43,6 +49,8 @@
#define TEGRA234_RESET_QSPI0 76U
#define TEGRA234_RESET_QSPI1 77U
#define TEGRA234_RESET_SDMMC4 85U
+#define TEGRA234_RESET_MGBE3_PCS 87U
+#define TEGRA234_RESET_MGBE3_MAC 88U
#define TEGRA234_RESET_UARTA 100U
#define TEGRA234_RESET_PEX0_CORE_0 116U
#define TEGRA234_RESET_PEX0_CORE_1 117U
--
2.36.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients
2022-07-07 7:48 [PATCH v4 0/9] tegra: Add support for MGBE controller Thierry Reding
2022-07-07 7:48 ` [PATCH v4 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Thierry Reding
2022-07-07 7:48 ` [PATCH v4 2/9] dt-bindings: Add Tegra234 MGBE clocks and resets Thierry Reding
@ 2022-07-07 7:48 ` Thierry Reding
2022-07-07 7:48 ` [PATCH v4 4/9] memory: tegra: Add MGBE memory clients for Tegra234 Thierry Reding
` (5 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Thierry Reding @ 2022-07-07 7:48 UTC (permalink / raw)
To: Thierry Reding
Cc: Jon Hunter, Rob Herring, Krzysztof Kozlowski, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Bhadram Varka,
devicetree, linux-tegra, netdev, Krzysztof Kozlowski
From: Thierry Reding <treding@nvidia.com>
Add the memory client and stream ID definitions for the Multi-Gigabit
Ethernet (MGBE) hardware found on NVIDIA Tegra234 SoCs.
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
include/dt-bindings/memory/tegra234-mc.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h
index e3b0e9da295d..c202e7642bbd 100644
--- a/include/dt-bindings/memory/tegra234-mc.h
+++ b/include/dt-bindings/memory/tegra234-mc.h
@@ -11,11 +11,15 @@
/* NISO0 stream IDs */
#define TEGRA234_SID_APE 0x02
#define TEGRA234_SID_HDA 0x03
+#define TEGRA234_SID_MGBE 0x06
#define TEGRA234_SID_PCIE0 0x12
#define TEGRA234_SID_PCIE4 0x13
#define TEGRA234_SID_PCIE5 0x14
#define TEGRA234_SID_PCIE6 0x15
#define TEGRA234_SID_PCIE9 0x1f
+#define TEGRA234_SID_MGBE_VF1 0x49
+#define TEGRA234_SID_MGBE_VF2 0x4a
+#define TEGRA234_SID_MGBE_VF3 0x4b
/* NISO1 stream IDs */
#define TEGRA234_SID_SDMMC4 0x02
@@ -61,8 +65,24 @@
#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48
/* PCIE7r1 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49
+/* MGBE0 read client */
+#define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58
+/* MGBEB read client */
+#define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59
+/* MGBEC read client */
+#define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a
+/* MGBED read client */
+#define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b
+/* MGBE0 write client */
+#define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c
+/* MGBEB write client */
+#define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f
+/* MGBEC write client */
+#define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61
/* sdmmcd memory read client */
#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
+/* MGBED write client */
+#define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65
/* sdmmcd memory write client */
#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
/* BPMP read client */
--
2.36.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 4/9] memory: tegra: Add MGBE memory clients for Tegra234
2022-07-07 7:48 [PATCH v4 0/9] tegra: Add support for MGBE controller Thierry Reding
` (2 preceding siblings ...)
2022-07-07 7:48 ` [PATCH v4 3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients Thierry Reding
@ 2022-07-07 7:48 ` Thierry Reding
2022-07-07 7:48 ` [PATCH v4 5/9] dt-bindings: net: Add Tegra234 MGBE Thierry Reding
` (4 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Thierry Reding @ 2022-07-07 7:48 UTC (permalink / raw)
To: Thierry Reding
Cc: Jon Hunter, Rob Herring, Krzysztof Kozlowski, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Bhadram Varka,
devicetree, linux-tegra, netdev, Krzysztof Kozlowski
From: Thierry Reding <treding@nvidia.com>
The NVIDIA Tegra234 SoC has multiple network interfaces with each their
own memory clients and stream IDs to allow for proper isolation.
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/memory/tegra/tegra234.c | 80 +++++++++++++++++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c
index e23ebd421f17..a9e8fd99730f 100644
--- a/drivers/memory/tegra/tegra234.c
+++ b/drivers/memory/tegra/tegra234.c
@@ -11,6 +11,76 @@
static const struct tegra_mc_client tegra234_mc_clients[] = {
{
+ .id = TEGRA234_MEMORY_CLIENT_MGBEARD,
+ .name = "mgbeard",
+ .sid = TEGRA234_SID_MGBE,
+ .regs = {
+ .sid = {
+ .override = 0x2c0,
+ .security = 0x2c4,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_MGBEBRD,
+ .name = "mgbebrd",
+ .sid = TEGRA234_SID_MGBE_VF1,
+ .regs = {
+ .sid = {
+ .override = 0x2c8,
+ .security = 0x2cc,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_MGBECRD,
+ .name = "mgbecrd",
+ .sid = TEGRA234_SID_MGBE_VF2,
+ .regs = {
+ .sid = {
+ .override = 0x2d0,
+ .security = 0x2d4,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_MGBEDRD,
+ .name = "mgbedrd",
+ .sid = TEGRA234_SID_MGBE_VF3,
+ .regs = {
+ .sid = {
+ .override = 0x2d8,
+ .security = 0x2dc,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_MGBEAWR,
+ .name = "mgbeawr",
+ .sid = TEGRA234_SID_MGBE,
+ .regs = {
+ .sid = {
+ .override = 0x2e0,
+ .security = 0x2e4,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_MGBEBWR,
+ .name = "mgbebwr",
+ .sid = TEGRA234_SID_MGBE_VF1,
+ .regs = {
+ .sid = {
+ .override = 0x2f8,
+ .security = 0x2fc,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_MGBECWR,
+ .name = "mgbecwr",
+ .sid = TEGRA234_SID_MGBE_VF2,
+ .regs = {
+ .sid = {
+ .override = 0x308,
+ .security = 0x30c,
+ },
+ },
+ }, {
.id = TEGRA234_MEMORY_CLIENT_SDMMCRAB,
.name = "sdmmcrab",
.sid = TEGRA234_SID_SDMMC4,
@@ -20,6 +90,16 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x31c,
},
},
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_MGBEDWR,
+ .name = "mgbedwr",
+ .sid = TEGRA234_SID_MGBE_VF3,
+ .regs = {
+ .sid = {
+ .override = 0x328,
+ .security = 0x32c,
+ },
+ },
}, {
.id = TEGRA234_MEMORY_CLIENT_SDMMCWAB,
.name = "sdmmcwab",
--
2.36.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 5/9] dt-bindings: net: Add Tegra234 MGBE
2022-07-07 7:48 [PATCH v4 0/9] tegra: Add support for MGBE controller Thierry Reding
` (3 preceding siblings ...)
2022-07-07 7:48 ` [PATCH v4 4/9] memory: tegra: Add MGBE memory clients for Tegra234 Thierry Reding
@ 2022-07-07 7:48 ` Thierry Reding
2022-07-08 16:26 ` Thierry Reding
2022-07-11 19:09 ` Rob Herring
2022-07-07 7:48 ` [PATCH v4 6/9] arm64: tegra: Add MGBE nodes on Tegra234 Thierry Reding
` (3 subsequent siblings)
8 siblings, 2 replies; 17+ messages in thread
From: Thierry Reding @ 2022-07-07 7:48 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Thierry Reding, Jon Hunter, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Bhadram Varka, devicetree,
linux-tegra, netdev
From: Bhadram Varka <vbhadram@nvidia.com>
Add device-tree binding documentation for the Multi-Gigabit Ethernet
(MGBE) controller found on NVIDIA Tegra234 SoCs.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v4:
- uses fixed lists of items for clock-names and reset-names
- add missing maxItems to interrupts property
- drop minItems where it equals maxItems
- drop unnecessary blank lines
- drop redundant comment
Changes in v3:
- add macsec and macsec-ns interrupt names
- improve mdio bus node description
- drop power-domains description
- improve bindings title
Changes in v2:
- add supported PHY modes
- change to dual license
.../bindings/net/nvidia,tegra234-mgbe.yaml | 162 ++++++++++++++++++
1 file changed, 162 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
diff --git a/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
new file mode 100644
index 000000000000..2bd3efff2485
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
+
+maintainers:
+ - Thierry Reding <treding@nvidia.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+ compatible:
+ const: nvidia,tegra234-mgbe
+
+ reg:
+ maxItems: 3
+
+ reg-names:
+ items:
+ - const: hypervisor
+ - const: mac
+ - const: xpcs
+
+ interrupts:
+ minItems: 1
+ maxItems: 3
+
+ interrupt-names:
+ minItems: 1
+ items:
+ - const: common
+ - const: macsec-ns
+ - const: macsec
+
+ clocks:
+ maxItems: 12
+
+ clock-names:
+ items:
+ - const: mgbe
+ - const: mac
+ - const: mac-divider
+ - const: ptp-ref
+ - const: rx-input-m
+ - const: rx-input
+ - const: tx
+ - const: eee-pcs
+ - const: rx-pcs-input
+ - const: rx-pcs-m
+ - const: rx-pcs
+ - const: tx-pcs
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: mac
+ - const: pcs
+
+ interconnects:
+ items:
+ - description: memory read client
+ - description: memory write client
+
+ interconnect-names:
+ items:
+ - const: dma-mem
+ - const: write
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ phy-handle: true
+
+ phy-mode:
+ contains:
+ enum:
+ - usxgmii
+ - 10gbase-kr
+
+ mdio:
+ $ref: mdio.yaml#
+ unevaluatedProperties: false
+ description:
+ Optional node for embedded MDIO controller.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - power-domains
+ - phy-handle
+ - phy-mode
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra234-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/memory/tegra234-mc.h>
+ #include <dt-bindings/power/tegra234-powergate.h>
+ #include <dt-bindings/reset/tegra234-reset.h>
+
+ ethernet@6800000 {
+ compatible = "nvidia,tegra234-mgbe";
+ reg = <0x06800000 0x10000>,
+ <0x06810000 0x10000>,
+ <0x068a0000 0x10000>;
+ reg-names = "hypervisor", "mac", "xpcs";
+ interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
+ <&bpmp TEGRA234_CLK_MGBE0_MAC>,
+ <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
+ <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE0_TX>,
+ <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
+ clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
+ "rx-pcs", "tx-pcs";
+ resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
+ <&bpmp TEGRA234_RESET_MGBE0_PCS>;
+ reset-names = "mac", "pcs";
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
+
+ phy-handle = <&mgbe0_phy>;
+ phy-mode = "usxgmii";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mgbe0_phy: phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+
+ #phy-cells = <0>;
+ };
+ };
+ };
--
2.36.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v4 5/9] dt-bindings: net: Add Tegra234 MGBE
2022-07-07 7:48 ` [PATCH v4 5/9] dt-bindings: net: Add Tegra234 MGBE Thierry Reding
@ 2022-07-08 16:26 ` Thierry Reding
2022-07-11 19:09 ` Rob Herring
1 sibling, 0 replies; 17+ messages in thread
From: Thierry Reding @ 2022-07-08 16:26 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Jon Hunter, David S . Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Bhadram Varka, devicetree, linux-tegra, netdev
[-- Attachment #1: Type: text/plain, Size: 6386 bytes --]
On Thu, Jul 07, 2022 at 09:48:14AM +0200, Thierry Reding wrote:
> From: Bhadram Varka <vbhadram@nvidia.com>
>
> Add device-tree binding documentation for the Multi-Gigabit Ethernet
> (MGBE) controller found on NVIDIA Tegra234 SoCs.
>
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v4:
> - uses fixed lists of items for clock-names and reset-names
> - add missing maxItems to interrupts property
> - drop minItems where it equals maxItems
> - drop unnecessary blank lines
> - drop redundant comment
>
> Changes in v3:
> - add macsec and macsec-ns interrupt names
> - improve mdio bus node description
> - drop power-domains description
> - improve bindings title
>
> Changes in v2:
> - add supported PHY modes
> - change to dual license
>
> .../bindings/net/nvidia,tegra234-mgbe.yaml | 162 ++++++++++++++++++
> 1 file changed, 162 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
Rob, Krzysztof,
any chance I could get a Reviewed-by/Acked-by on this? I'd like to
include patches 5-8 as part of the ARM-SoC PRs for v5.20 (which I need
to send before v5.19-rc6) because it unblocks a number of people and
with networking support we could enable more of our daily testing
coverage.
Thanks,
Thierry
> diff --git a/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
> new file mode 100644
> index 000000000000..2bd3efff2485
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
> @@ -0,0 +1,162 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
> +
> +maintainers:
> + - Thierry Reding <treding@nvidia.com>
> + - Jon Hunter <jonathanh@nvidia.com>
> +
> +properties:
> + compatible:
> + const: nvidia,tegra234-mgbe
> +
> + reg:
> + maxItems: 3
> +
> + reg-names:
> + items:
> + - const: hypervisor
> + - const: mac
> + - const: xpcs
> +
> + interrupts:
> + minItems: 1
> + maxItems: 3
> +
> + interrupt-names:
> + minItems: 1
> + items:
> + - const: common
> + - const: macsec-ns
> + - const: macsec
> +
> + clocks:
> + maxItems: 12
> +
> + clock-names:
> + items:
> + - const: mgbe
> + - const: mac
> + - const: mac-divider
> + - const: ptp-ref
> + - const: rx-input-m
> + - const: rx-input
> + - const: tx
> + - const: eee-pcs
> + - const: rx-pcs-input
> + - const: rx-pcs-m
> + - const: rx-pcs
> + - const: tx-pcs
> +
> + resets:
> + maxItems: 2
> +
> + reset-names:
> + items:
> + - const: mac
> + - const: pcs
> +
> + interconnects:
> + items:
> + - description: memory read client
> + - description: memory write client
> +
> + interconnect-names:
> + items:
> + - const: dma-mem
> + - const: write
> +
> + iommus:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + phy-handle: true
> +
> + phy-mode:
> + contains:
> + enum:
> + - usxgmii
> + - 10gbase-kr
> +
> + mdio:
> + $ref: mdio.yaml#
> + unevaluatedProperties: false
> + description:
> + Optional node for embedded MDIO controller.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-names
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - power-domains
> + - phy-handle
> + - phy-mode
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/tegra234-clock.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/memory/tegra234-mc.h>
> + #include <dt-bindings/power/tegra234-powergate.h>
> + #include <dt-bindings/reset/tegra234-reset.h>
> +
> + ethernet@6800000 {
> + compatible = "nvidia,tegra234-mgbe";
> + reg = <0x06800000 0x10000>,
> + <0x06810000 0x10000>,
> + <0x068a0000 0x10000>;
> + reg-names = "hypervisor", "mac", "xpcs";
> + interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "common";
> + clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
> + <&bpmp TEGRA234_CLK_MGBE0_MAC>,
> + <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
> + <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
> + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
> + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
> + <&bpmp TEGRA234_CLK_MGBE0_TX>,
> + <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
> + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
> + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
> + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
> + <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
> + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
> + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
> + "rx-pcs", "tx-pcs";
> + resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
> + <&bpmp TEGRA234_RESET_MGBE0_PCS>;
> + reset-names = "mac", "pcs";
> + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
> + <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
> + interconnect-names = "dma-mem", "write";
> + iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
> + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
> +
> + phy-handle = <&mgbe0_phy>;
> + phy-mode = "usxgmii";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mgbe0_phy: phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + reg = <0x0>;
> +
> + #phy-cells = <0>;
> + };
> + };
> + };
> --
> 2.36.1
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v4 5/9] dt-bindings: net: Add Tegra234 MGBE
2022-07-07 7:48 ` [PATCH v4 5/9] dt-bindings: net: Add Tegra234 MGBE Thierry Reding
2022-07-08 16:26 ` Thierry Reding
@ 2022-07-11 19:09 ` Rob Herring
1 sibling, 0 replies; 17+ messages in thread
From: Rob Herring @ 2022-07-11 19:09 UTC (permalink / raw)
To: Thierry Reding
Cc: Bhadram Varka, Paolo Abeni, devicetree, David S . Miller,
Krzysztof Kozlowski, Jon Hunter, Eric Dumazet, Jakub Kicinski,
netdev, linux-tegra, Rob Herring
On Thu, 07 Jul 2022 09:48:14 +0200, Thierry Reding wrote:
> From: Bhadram Varka <vbhadram@nvidia.com>
>
> Add device-tree binding documentation for the Multi-Gigabit Ethernet
> (MGBE) controller found on NVIDIA Tegra234 SoCs.
>
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v4:
> - uses fixed lists of items for clock-names and reset-names
> - add missing maxItems to interrupts property
> - drop minItems where it equals maxItems
> - drop unnecessary blank lines
> - drop redundant comment
>
> Changes in v3:
> - add macsec and macsec-ns interrupt names
> - improve mdio bus node description
> - drop power-domains description
> - improve bindings title
>
> Changes in v2:
> - add supported PHY modes
> - change to dual license
>
> .../bindings/net/nvidia,tegra234-mgbe.yaml | 162 ++++++++++++++++++
> 1 file changed, 162 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v4 6/9] arm64: tegra: Add MGBE nodes on Tegra234
2022-07-07 7:48 [PATCH v4 0/9] tegra: Add support for MGBE controller Thierry Reding
` (4 preceding siblings ...)
2022-07-07 7:48 ` [PATCH v4 5/9] dt-bindings: net: Add Tegra234 MGBE Thierry Reding
@ 2022-07-07 7:48 ` Thierry Reding
2022-07-07 7:48 ` [PATCH v4 7/9] arm64: tegra: Enable MGBE on Jetson AGX Orin Developer Kit Thierry Reding
` (2 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Thierry Reding @ 2022-07-07 7:48 UTC (permalink / raw)
To: Thierry Reding
Cc: Jon Hunter, Rob Herring, Krzysztof Kozlowski, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Bhadram Varka,
devicetree, linux-tegra, netdev
From: Thierry Reding <treding@nvidia.com>
Add device tree nodes for the four instances of the Multi-Gigabit
Ethernet (MGBE) IP found on NVIDIA Tegra234 SoCs.
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 136 +++++++++++++++++++++++
1 file changed, 136 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index cb3af539e477..b77b55e80223 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -791,6 +791,142 @@ hsp_top0: hsp@3c00000 {
#mbox-cells = <2>;
};
+ ethernet@6800000 {
+ compatible = "nvidia,tegra234-mgbe";
+ reg = <0x06800000 0x10000>,
+ <0x06810000 0x10000>,
+ <0x068a0000 0x10000>;
+ reg-names = "hypervisor", "mac", "xpcs";
+ interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
+ <&bpmp TEGRA234_CLK_MGBE0_MAC>,
+ <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
+ <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE0_TX>,
+ <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
+ clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
+ "rx-pcs", "tx-pcs";
+ resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
+ <&bpmp TEGRA234_RESET_MGBE0_PCS>;
+ reset-names = "mac", "pcs";
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
+ status = "disabled";
+ };
+
+ ethernet@6900000 {
+ compatible = "nvidia,tegra234-mgbe";
+ reg = <0x06900000 0x10000>,
+ <0x06910000 0x10000>,
+ <0x069a0000 0x10000>;
+ reg-names = "hypervisor", "mac", "xpcs";
+ interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>,
+ <&bpmp TEGRA234_CLK_MGBE1_MAC>,
+ <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>,
+ <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>,
+ <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>,
+ <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE1_TX>,
+ <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,
+ <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;
+ clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
+ "rx-pcs", "tx-pcs";
+ resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,
+ <&bpmp TEGRA234_RESET_MGBE1_PCS>;
+ reset-names = "mac", "pcs";
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>;
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
+ status = "disabled";
+ };
+
+ ethernet@6a00000 {
+ compatible = "nvidia,tegra234-mgbe";
+ reg = <0x06a00000 0x10000>,
+ <0x06a10000 0x10000>,
+ <0x06aa0000 0x10000>;
+ reg-names = "hypervisor", "mac", "xpcs";
+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>,
+ <&bpmp TEGRA234_CLK_MGBE2_MAC>,
+ <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>,
+ <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>,
+ <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>,
+ <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE2_TX>,
+ <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,
+ <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;
+ clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
+ "rx-pcs", "tx-pcs";
+ resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,
+ <&bpmp TEGRA234_RESET_MGBE2_PCS>;
+ reset-names = "mac", "pcs";
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>;
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
+ status = "disabled";
+ };
+
+ ethernet@6b00000 {
+ compatible = "nvidia,tegra234-mgbe";
+ reg = <0x06b00000 0x10000>,
+ <0x06b10000 0x10000>,
+ <0x06ba0000 0x10000>;
+ reg-names = "hypervisor", "mac", "xpcs";
+ interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>,
+ <&bpmp TEGRA234_CLK_MGBE3_MAC>,
+ <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>,
+ <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>,
+ <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>,
+ <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE3_TX>,
+ <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,
+ <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;
+ clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
+ "rx-pcs", "tx-pcs";
+ resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,
+ <&bpmp TEGRA234_RESET_MGBE3_PCS>;
+ reset-names = "mac", "pcs";
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>;
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
+ status = "disabled";
+ };
+
smmu_niso1: iommu@8000000 {
compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
reg = <0x8000000 0x1000000>,
--
2.36.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 7/9] arm64: tegra: Enable MGBE on Jetson AGX Orin Developer Kit
2022-07-07 7:48 [PATCH v4 0/9] tegra: Add support for MGBE controller Thierry Reding
` (5 preceding siblings ...)
2022-07-07 7:48 ` [PATCH v4 6/9] arm64: tegra: Add MGBE nodes on Tegra234 Thierry Reding
@ 2022-07-07 7:48 ` Thierry Reding
2022-07-07 7:48 ` [PATCH v4 8/9] arm64: defconfig: Enable Tegra MGBE driver Thierry Reding
2022-07-07 7:48 ` [PATCH net-next v4 9/9] stmmac: tegra: Add MGBE support Thierry Reding
8 siblings, 0 replies; 17+ messages in thread
From: Thierry Reding @ 2022-07-07 7:48 UTC (permalink / raw)
To: Thierry Reding
Cc: Jon Hunter, Rob Herring, Krzysztof Kozlowski, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Bhadram Varka,
devicetree, linux-tegra, netdev
From: Thierry Reding <treding@nvidia.com>
A Multi-Gigabit Ethernet (MGBE) instance drives the primary Ethernet
port on the Jetson AGX Orin Developer Kit. Enable it.
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../nvidia/tegra234-p3737-0000+p3701-0000.dts | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
index eaf1994abb04..8e2618a902ab 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
@@ -1976,6 +1976,27 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ bus@0 {
+ ethernet@6800000 {
+ status = "okay";
+
+ phy-handle = <&mgbe0_phy>;
+ phy-mode = "usxgmii";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mgbe0_phy: phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+
+ #phy-cells = <0>;
+ };
+ };
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
status = "okay";
--
2.36.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 8/9] arm64: defconfig: Enable Tegra MGBE driver
2022-07-07 7:48 [PATCH v4 0/9] tegra: Add support for MGBE controller Thierry Reding
` (6 preceding siblings ...)
2022-07-07 7:48 ` [PATCH v4 7/9] arm64: tegra: Enable MGBE on Jetson AGX Orin Developer Kit Thierry Reding
@ 2022-07-07 7:48 ` Thierry Reding
2022-07-07 7:48 ` [PATCH net-next v4 9/9] stmmac: tegra: Add MGBE support Thierry Reding
8 siblings, 0 replies; 17+ messages in thread
From: Thierry Reding @ 2022-07-07 7:48 UTC (permalink / raw)
To: Thierry Reding
Cc: Jon Hunter, Rob Herring, Krzysztof Kozlowski, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Bhadram Varka,
devicetree, linux-tegra, netdev
From: Bhadram Varka <vbhadram@nvidia.com>
Enable the driver for the Multi-Gigabit Ethernet (MGBE) controller which
can be found on NVIDIA Tegra234 SoCs.
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 7d1105343bc2..f80142abd9c6 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -359,6 +359,7 @@ CONFIG_SMSC911X=y
CONFIG_SNI_AVE=y
CONFIG_SNI_NETSEC=y
CONFIG_STMMAC_ETH=m
+CONFIG_DWMAC_TEGRA=m
CONFIG_TI_K3_AM65_CPSW_NUSS=y
CONFIG_QCOM_IPA=m
CONFIG_MESON_GXL_PHY=m
--
2.36.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH net-next v4 9/9] stmmac: tegra: Add MGBE support
2022-07-07 7:48 [PATCH v4 0/9] tegra: Add support for MGBE controller Thierry Reding
` (7 preceding siblings ...)
2022-07-07 7:48 ` [PATCH v4 8/9] arm64: defconfig: Enable Tegra MGBE driver Thierry Reding
@ 2022-07-07 7:48 ` Thierry Reding
2022-09-07 16:36 ` Thierry Reding
8 siblings, 1 reply; 17+ messages in thread
From: Thierry Reding @ 2022-07-07 7:48 UTC (permalink / raw)
To: David S . Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni
Cc: Thierry Reding, Jon Hunter, Rob Herring, Krzysztof Kozlowski,
Bhadram Varka, devicetree, linux-tegra, netdev
From: Bhadram Varka <vbhadram@nvidia.com>
Add support for the Multi-Gigabit Ethernet (MGBE/XPCS) IP found on
NVIDIA Tegra234 SoCs.
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Note that this doesn't have any dependencies on any of the patches
earlier in the series, so this can be applied independently.
drivers/net/ethernet/stmicro/stmmac/Kconfig | 6 +
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
.../net/ethernet/stmicro/stmmac/dwmac-tegra.c | 290 ++++++++++++++++++
3 files changed, 297 insertions(+)
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 929cfc22cd0c..47af5a59ce88 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -232,6 +232,12 @@ config DWMAC_INTEL_PLAT
the stmmac device driver. This driver is used for the Intel Keem Bay
SoC.
+config DWMAC_TEGRA
+ tristate "NVIDIA Tegra MGBE support"
+ depends on ARCH_TEGRA || COMPILE_TEST
+ help
+ Support for the MGBE controller found on Tegra SoCs.
+
config DWMAC_VISCONTI
tristate "Toshiba Visconti DWMAC support"
default ARCH_VISCONTI
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index d4e12e9ace4f..057e4bab5c08 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o
obj-$(CONFIG_DWMAC_INTEL_PLAT) += dwmac-intel-plat.o
obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o
obj-$(CONFIG_DWMAC_IMX8) += dwmac-imx.o
+obj-$(CONFIG_DWMAC_TEGRA) += dwmac-tegra.o
obj-$(CONFIG_DWMAC_VISCONTI) += dwmac-visconti.o
stmmac-platform-objs:= stmmac_platform.o
dwmac-altr-socfpga-objs := altr_tse_pcs.o dwmac-socfpga.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
new file mode 100644
index 000000000000..bb4b540820fa
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
@@ -0,0 +1,290 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+#include <linux/module.h>
+#include <linux/stmmac.h>
+#include <linux/clk.h>
+
+#include "stmmac_platform.h"
+
+static const char *const mgbe_clks[] = {
+ "rx-pcs", "tx", "tx-pcs", "mac-divider", "mac", "mgbe", "ptp-ref", "mac"
+};
+
+struct tegra_mgbe {
+ struct device *dev;
+
+ struct clk_bulk_data *clks;
+
+ struct reset_control *rst_mac;
+ struct reset_control *rst_pcs;
+
+ void __iomem *hv;
+ void __iomem *regs;
+ void __iomem *xpcs;
+
+ struct mii_bus *mii;
+};
+
+#define XPCS_WRAP_UPHY_RX_CONTROL 0x801c
+#define XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD BIT(31)
+#define XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY BIT(10)
+#define XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET BIT(9)
+#define XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN BIT(8)
+#define XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP (BIT(7) | BIT(6))
+#define XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ BIT(5)
+#define XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ BIT(4)
+#define XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN BIT(0)
+#define XPCS_WRAP_UPHY_HW_INIT_CTRL 0x8020
+#define XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN BIT(0)
+#define XPCS_WRAP_UPHY_HW_INIT_CTRL_RX_EN BIT(2)
+#define XPCS_WRAP_UPHY_STATUS 0x8044
+#define XPCS_WRAP_UPHY_STATUS_TX_P_UP BIT(0)
+#define XPCS_WRAP_IRQ_STATUS 0x8050
+#define XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS BIT(6)
+
+#define XPCS_REG_ADDR_SHIFT 10
+#define XPCS_REG_ADDR_MASK 0x1fff
+#define XPCS_ADDR 0x3fc
+
+#define MGBE_WRAP_COMMON_INTR_ENABLE 0x8704
+#define MAC_SBD_INTR BIT(2)
+#define MGBE_WRAP_AXI_ASID0_CTRL 0x8400
+#define MGBE_SID 0x6
+
+static void mgbe_uphy_lane_bringup(struct tegra_mgbe *mgbe)
+{
+ unsigned int retry = 300;
+ u32 value;
+ int err;
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS);
+ if ((value & XPCS_WRAP_UPHY_STATUS_TX_P_UP) == 0) {
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
+ value |= XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
+ }
+
+ err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value,
+ (value & XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN) == 0,
+ 500, 500 * 2000);
+ if (err < 0)
+ dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n");
+
+ usleep_range(10000, 20000);
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+ value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+ value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+ value &= ~XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+ value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+ value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+
+ err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL, value,
+ (value & XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN) == 0,
+ 1000, 1000 * 2000);
+ if (err < 0)
+ dev_err(mgbe->dev, "timeout waiting for RX calibration to become enabled\n");
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+ value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+ value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+ value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+ value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+
+ while (--retry) {
+ err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_IRQ_STATUS, value,
+ value & XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS,
+ 500, 500 * 2000);
+ if (err < 0) {
+ dev_err(mgbe->dev, "timeout waiting for link to become ready\n");
+ usleep_range(10000, 20000);
+ continue;
+ }
+ break;
+ }
+
+ /* clear status */
+ writel(value, mgbe->xpcs + XPCS_WRAP_IRQ_STATUS);
+}
+
+static int tegra_mgbe_probe(struct platform_device *pdev)
+{
+ struct plat_stmmacenet_data *plat;
+ struct stmmac_resources res;
+ struct tegra_mgbe *mgbe;
+ int irq, err, i;
+
+ mgbe = devm_kzalloc(&pdev->dev, sizeof(*mgbe), GFP_KERNEL);
+ if (!mgbe)
+ return -ENOMEM;
+
+ mgbe->dev = &pdev->dev;
+
+ memset(&res, 0, sizeof(res));
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ mgbe->hv = devm_platform_ioremap_resource_byname(pdev, "hypervisor");
+ if (IS_ERR(mgbe->hv))
+ return PTR_ERR(mgbe->hv);
+
+ mgbe->regs = devm_platform_ioremap_resource_byname(pdev, "mac");
+ if (IS_ERR(mgbe->regs))
+ return PTR_ERR(mgbe->regs);
+
+ mgbe->xpcs = devm_platform_ioremap_resource_byname(pdev, "xpcs");
+ if (IS_ERR(mgbe->xpcs))
+ return PTR_ERR(mgbe->xpcs);
+
+ res.addr = mgbe->regs;
+ res.irq = irq;
+
+ mgbe->clks = devm_kzalloc(&pdev->dev, sizeof(*mgbe->clks), GFP_KERNEL);
+ if (!mgbe->clks)
+ return -ENOMEM;
+
+ for (i = 0; i < ARRAY_SIZE(mgbe_clks); i++)
+ mgbe->clks[i].id = mgbe_clks[i];
+
+ err = devm_clk_bulk_get(mgbe->dev, ARRAY_SIZE(mgbe_clks), mgbe->clks);
+ if (err < 0)
+ return err;
+
+ err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks);
+ if (err < 0)
+ return err;
+
+ /* Perform MAC reset */
+ mgbe->rst_mac = devm_reset_control_get(&pdev->dev, "mac");
+ if (IS_ERR(mgbe->rst_mac))
+ return PTR_ERR(mgbe->rst_mac);
+
+ err = reset_control_assert(mgbe->rst_mac);
+ if (err < 0)
+ return err;
+
+ usleep_range(2000, 4000);
+
+ err = reset_control_deassert(mgbe->rst_mac);
+ if (err < 0)
+ return err;
+
+ /* Perform PCS reset */
+ mgbe->rst_pcs = devm_reset_control_get(&pdev->dev, "pcs");
+ if (IS_ERR(mgbe->rst_pcs))
+ return PTR_ERR(mgbe->rst_pcs);
+
+ err = reset_control_assert(mgbe->rst_pcs);
+ if (err < 0)
+ return err;
+
+ usleep_range(2000, 4000);
+
+ err = reset_control_deassert(mgbe->rst_pcs);
+ if (err < 0)
+ return err;
+
+ plat = stmmac_probe_config_dt(pdev, res.mac);
+ if (IS_ERR(plat))
+ return PTR_ERR(plat);
+
+ plat->has_xgmac = 1;
+ plat->tso_en = 1;
+ plat->pmt = 1;
+ plat->bsp_priv = mgbe;
+
+ if (!plat->mdio_node)
+ plat->mdio_node = of_get_child_by_name(pdev->dev.of_node, "mdio");
+
+ if (!plat->mdio_bus_data) {
+ plat->mdio_bus_data = devm_kzalloc(&pdev->dev, sizeof(*plat->mdio_bus_data),
+ GFP_KERNEL);
+ if (!plat->mdio_bus_data) {
+ err = -ENOMEM;
+ goto remove;
+ }
+ }
+
+ plat->mdio_bus_data->needs_reset = true;
+
+ mgbe_uphy_lane_bringup(mgbe);
+
+ /* Tx FIFO Size - 128KB */
+ plat->tx_fifo_size = 131072;
+ /* Rx FIFO Size - 192KB */
+ plat->rx_fifo_size = 196608;
+
+ /* Enable common interrupt at wrapper level */
+ writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE);
+
+ /* Program SID */
+ writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL);
+
+ err = stmmac_dvr_probe(&pdev->dev, plat, &res);
+ if (err < 0)
+ goto remove;
+
+ return 0;
+
+remove:
+ stmmac_remove_config_dt(pdev, plat);
+ return err;
+}
+
+static int tegra_mgbe_remove(struct platform_device *pdev)
+{
+ struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(&pdev->dev);
+
+ clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);
+
+ stmmac_pltfr_remove(pdev);
+
+ return 0;
+}
+
+static const struct of_device_id tegra_mgbe_match[] = {
+ { .compatible = "nvidia,tegra234-mgbe", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, tegra_mgbe_match);
+
+static struct platform_driver tegra_mgbe_driver = {
+ .probe = tegra_mgbe_probe,
+ .remove = tegra_mgbe_remove,
+ .driver = {
+ .name = "tegra-mgbe",
+ .pm = &stmmac_pltfr_pm_ops,
+ .of_match_table = tegra_mgbe_match,
+ },
+};
+module_platform_driver(tegra_mgbe_driver);
+
+MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
+MODULE_DESCRIPTION("NVIDIA Tegra MGBE driver");
+MODULE_LICENSE("GPL");
--
2.36.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH net-next v4 9/9] stmmac: tegra: Add MGBE support
2022-07-07 7:48 ` [PATCH net-next v4 9/9] stmmac: tegra: Add MGBE support Thierry Reding
@ 2022-09-07 16:36 ` Thierry Reding
2022-09-22 15:05 ` Jon Hunter
0 siblings, 1 reply; 17+ messages in thread
From: Thierry Reding @ 2022-09-07 16:36 UTC (permalink / raw)
To: David S . Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni
Cc: Jon Hunter, Rob Herring, Krzysztof Kozlowski, Bhadram Varka,
devicetree, linux-tegra, netdev
[-- Attachment #1: Type: text/plain, Size: 11753 bytes --]
On Thu, Jul 07, 2022 at 09:48:18AM +0200, Thierry Reding wrote:
> From: Bhadram Varka <vbhadram@nvidia.com>
>
> Add support for the Multi-Gigabit Ethernet (MGBE/XPCS) IP found on
> NVIDIA Tegra234 SoCs.
>
> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Note that this doesn't have any dependencies on any of the patches
> earlier in the series, so this can be applied independently.
>
> drivers/net/ethernet/stmicro/stmmac/Kconfig | 6 +
> drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
> .../net/ethernet/stmicro/stmmac/dwmac-tegra.c | 290 ++++++++++++++++++
> 3 files changed, 297 insertions(+)
> create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
Patches 1-8 of this have already been applied to the Tegra tree. Are
there any more comments on this or can this be merged as well?
From a Tegra point of view this looks good, so:
Acked-by: Thierry Reding <treding@nvidia.com>
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
> index 929cfc22cd0c..47af5a59ce88 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
> +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
> @@ -232,6 +232,12 @@ config DWMAC_INTEL_PLAT
> the stmmac device driver. This driver is used for the Intel Keem Bay
> SoC.
>
> +config DWMAC_TEGRA
> + tristate "NVIDIA Tegra MGBE support"
> + depends on ARCH_TEGRA || COMPILE_TEST
> + help
> + Support for the MGBE controller found on Tegra SoCs.
> +
> config DWMAC_VISCONTI
> tristate "Toshiba Visconti DWMAC support"
> default ARCH_VISCONTI
> diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
> index d4e12e9ace4f..057e4bab5c08 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/Makefile
> +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
> @@ -31,6 +31,7 @@ obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o
> obj-$(CONFIG_DWMAC_INTEL_PLAT) += dwmac-intel-plat.o
> obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o
> obj-$(CONFIG_DWMAC_IMX8) += dwmac-imx.o
> +obj-$(CONFIG_DWMAC_TEGRA) += dwmac-tegra.o
> obj-$(CONFIG_DWMAC_VISCONTI) += dwmac-visconti.o
> stmmac-platform-objs:= stmmac_platform.o
> dwmac-altr-socfpga-objs := altr_tse_pcs.o dwmac-socfpga.o
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
> new file mode 100644
> index 000000000000..bb4b540820fa
> --- /dev/null
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
> @@ -0,0 +1,290 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +#include <linux/platform_device.h>
> +#include <linux/of_device.h>
> +#include <linux/module.h>
> +#include <linux/stmmac.h>
> +#include <linux/clk.h>
> +
> +#include "stmmac_platform.h"
> +
> +static const char *const mgbe_clks[] = {
> + "rx-pcs", "tx", "tx-pcs", "mac-divider", "mac", "mgbe", "ptp-ref", "mac"
> +};
> +
> +struct tegra_mgbe {
> + struct device *dev;
> +
> + struct clk_bulk_data *clks;
> +
> + struct reset_control *rst_mac;
> + struct reset_control *rst_pcs;
> +
> + void __iomem *hv;
> + void __iomem *regs;
> + void __iomem *xpcs;
> +
> + struct mii_bus *mii;
> +};
> +
> +#define XPCS_WRAP_UPHY_RX_CONTROL 0x801c
> +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD BIT(31)
> +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY BIT(10)
> +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET BIT(9)
> +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN BIT(8)
> +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP (BIT(7) | BIT(6))
> +#define XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ BIT(5)
> +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ BIT(4)
> +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN BIT(0)
> +#define XPCS_WRAP_UPHY_HW_INIT_CTRL 0x8020
> +#define XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN BIT(0)
> +#define XPCS_WRAP_UPHY_HW_INIT_CTRL_RX_EN BIT(2)
> +#define XPCS_WRAP_UPHY_STATUS 0x8044
> +#define XPCS_WRAP_UPHY_STATUS_TX_P_UP BIT(0)
> +#define XPCS_WRAP_IRQ_STATUS 0x8050
> +#define XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS BIT(6)
> +
> +#define XPCS_REG_ADDR_SHIFT 10
> +#define XPCS_REG_ADDR_MASK 0x1fff
> +#define XPCS_ADDR 0x3fc
> +
> +#define MGBE_WRAP_COMMON_INTR_ENABLE 0x8704
> +#define MAC_SBD_INTR BIT(2)
> +#define MGBE_WRAP_AXI_ASID0_CTRL 0x8400
> +#define MGBE_SID 0x6
> +
> +static void mgbe_uphy_lane_bringup(struct tegra_mgbe *mgbe)
> +{
> + unsigned int retry = 300;
> + u32 value;
> + int err;
> +
> + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS);
> + if ((value & XPCS_WRAP_UPHY_STATUS_TX_P_UP) == 0) {
> + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
> + value |= XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN;
> + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
> + }
> +
> + err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value,
> + (value & XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN) == 0,
> + 500, 500 * 2000);
> + if (err < 0)
> + dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n");
> +
> + usleep_range(10000, 20000);
> +
> + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD;
> + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> +
> + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> + value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ;
> + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> +
> + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> + value &= ~XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ;
> + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> +
> + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> + value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP;
> + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> +
> + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN;
> + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> +
> + err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL, value,
> + (value & XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN) == 0,
> + 1000, 1000 * 2000);
> + if (err < 0)
> + dev_err(mgbe->dev, "timeout waiting for RX calibration to become enabled\n");
> +
> + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN;
> + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> +
> + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET;
> + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> +
> + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> + value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET;
> + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> +
> + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY;
> + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
> +
> + while (--retry) {
> + err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_IRQ_STATUS, value,
> + value & XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS,
> + 500, 500 * 2000);
> + if (err < 0) {
> + dev_err(mgbe->dev, "timeout waiting for link to become ready\n");
> + usleep_range(10000, 20000);
> + continue;
> + }
> + break;
> + }
> +
> + /* clear status */
> + writel(value, mgbe->xpcs + XPCS_WRAP_IRQ_STATUS);
> +}
> +
> +static int tegra_mgbe_probe(struct platform_device *pdev)
> +{
> + struct plat_stmmacenet_data *plat;
> + struct stmmac_resources res;
> + struct tegra_mgbe *mgbe;
> + int irq, err, i;
> +
> + mgbe = devm_kzalloc(&pdev->dev, sizeof(*mgbe), GFP_KERNEL);
> + if (!mgbe)
> + return -ENOMEM;
> +
> + mgbe->dev = &pdev->dev;
> +
> + memset(&res, 0, sizeof(res));
> +
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0)
> + return irq;
> +
> + mgbe->hv = devm_platform_ioremap_resource_byname(pdev, "hypervisor");
> + if (IS_ERR(mgbe->hv))
> + return PTR_ERR(mgbe->hv);
> +
> + mgbe->regs = devm_platform_ioremap_resource_byname(pdev, "mac");
> + if (IS_ERR(mgbe->regs))
> + return PTR_ERR(mgbe->regs);
> +
> + mgbe->xpcs = devm_platform_ioremap_resource_byname(pdev, "xpcs");
> + if (IS_ERR(mgbe->xpcs))
> + return PTR_ERR(mgbe->xpcs);
> +
> + res.addr = mgbe->regs;
> + res.irq = irq;
> +
> + mgbe->clks = devm_kzalloc(&pdev->dev, sizeof(*mgbe->clks), GFP_KERNEL);
> + if (!mgbe->clks)
> + return -ENOMEM;
> +
> + for (i = 0; i < ARRAY_SIZE(mgbe_clks); i++)
> + mgbe->clks[i].id = mgbe_clks[i];
> +
> + err = devm_clk_bulk_get(mgbe->dev, ARRAY_SIZE(mgbe_clks), mgbe->clks);
> + if (err < 0)
> + return err;
> +
> + err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks);
> + if (err < 0)
> + return err;
> +
> + /* Perform MAC reset */
> + mgbe->rst_mac = devm_reset_control_get(&pdev->dev, "mac");
> + if (IS_ERR(mgbe->rst_mac))
> + return PTR_ERR(mgbe->rst_mac);
> +
> + err = reset_control_assert(mgbe->rst_mac);
> + if (err < 0)
> + return err;
> +
> + usleep_range(2000, 4000);
> +
> + err = reset_control_deassert(mgbe->rst_mac);
> + if (err < 0)
> + return err;
> +
> + /* Perform PCS reset */
> + mgbe->rst_pcs = devm_reset_control_get(&pdev->dev, "pcs");
> + if (IS_ERR(mgbe->rst_pcs))
> + return PTR_ERR(mgbe->rst_pcs);
> +
> + err = reset_control_assert(mgbe->rst_pcs);
> + if (err < 0)
> + return err;
> +
> + usleep_range(2000, 4000);
> +
> + err = reset_control_deassert(mgbe->rst_pcs);
> + if (err < 0)
> + return err;
> +
> + plat = stmmac_probe_config_dt(pdev, res.mac);
> + if (IS_ERR(plat))
> + return PTR_ERR(plat);
> +
> + plat->has_xgmac = 1;
> + plat->tso_en = 1;
> + plat->pmt = 1;
> + plat->bsp_priv = mgbe;
> +
> + if (!plat->mdio_node)
> + plat->mdio_node = of_get_child_by_name(pdev->dev.of_node, "mdio");
> +
> + if (!plat->mdio_bus_data) {
> + plat->mdio_bus_data = devm_kzalloc(&pdev->dev, sizeof(*plat->mdio_bus_data),
> + GFP_KERNEL);
> + if (!plat->mdio_bus_data) {
> + err = -ENOMEM;
> + goto remove;
> + }
> + }
> +
> + plat->mdio_bus_data->needs_reset = true;
> +
> + mgbe_uphy_lane_bringup(mgbe);
> +
> + /* Tx FIFO Size - 128KB */
> + plat->tx_fifo_size = 131072;
> + /* Rx FIFO Size - 192KB */
> + plat->rx_fifo_size = 196608;
> +
> + /* Enable common interrupt at wrapper level */
> + writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE);
> +
> + /* Program SID */
> + writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL);
> +
> + err = stmmac_dvr_probe(&pdev->dev, plat, &res);
> + if (err < 0)
> + goto remove;
> +
> + return 0;
> +
> +remove:
> + stmmac_remove_config_dt(pdev, plat);
> + return err;
> +}
> +
> +static int tegra_mgbe_remove(struct platform_device *pdev)
> +{
> + struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(&pdev->dev);
> +
> + clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);
> +
> + stmmac_pltfr_remove(pdev);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id tegra_mgbe_match[] = {
> + { .compatible = "nvidia,tegra234-mgbe", },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, tegra_mgbe_match);
> +
> +static struct platform_driver tegra_mgbe_driver = {
> + .probe = tegra_mgbe_probe,
> + .remove = tegra_mgbe_remove,
> + .driver = {
> + .name = "tegra-mgbe",
> + .pm = &stmmac_pltfr_pm_ops,
> + .of_match_table = tegra_mgbe_match,
> + },
> +};
> +module_platform_driver(tegra_mgbe_driver);
> +
> +MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
> +MODULE_DESCRIPTION("NVIDIA Tegra MGBE driver");
> +MODULE_LICENSE("GPL");
> --
> 2.36.1
>
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^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH net-next v4 9/9] stmmac: tegra: Add MGBE support
2022-09-07 16:36 ` Thierry Reding
@ 2022-09-22 15:05 ` Jon Hunter
2022-09-22 15:34 ` Jakub Kicinski
0 siblings, 1 reply; 17+ messages in thread
From: Jon Hunter @ 2022-09-22 15:05 UTC (permalink / raw)
To: Thierry Reding, David S . Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu
Cc: Rob Herring, Krzysztof Kozlowski, Bhadram Varka, devicetree,
linux-tegra, netdev
Hi David, Jakub,
On 07/09/2022 17:36, Thierry Reding wrote:
> On Thu, Jul 07, 2022 at 09:48:18AM +0200, Thierry Reding wrote:
>> From: Bhadram Varka <vbhadram@nvidia.com>
>>
>> Add support for the Multi-Gigabit Ethernet (MGBE/XPCS) IP found on
>> NVIDIA Tegra234 SoCs.
>>
>> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
>> Signed-off-by: Thierry Reding <treding@nvidia.com>
>> ---
>> Note that this doesn't have any dependencies on any of the patches
>> earlier in the series, so this can be applied independently.
>>
>> drivers/net/ethernet/stmicro/stmmac/Kconfig | 6 +
>> drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
>> .../net/ethernet/stmicro/stmmac/dwmac-tegra.c | 290 ++++++++++++++++++
>> 3 files changed, 297 insertions(+)
>> create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
>
> Patches 1-8 of this have already been applied to the Tegra tree. Are
> there any more comments on this or can this be merged as well?
>
> From a Tegra point of view this looks good, so:
>
> Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Please can we queue this for v6.1? I have added the stmmac maintainers
to the email, but not sure if you can pick this up?
Thanks!
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH net-next v4 9/9] stmmac: tegra: Add MGBE support
2022-09-22 15:05 ` Jon Hunter
@ 2022-09-22 15:34 ` Jakub Kicinski
2022-09-23 12:39 ` Thierry Reding
0 siblings, 1 reply; 17+ messages in thread
From: Jakub Kicinski @ 2022-09-22 15:34 UTC (permalink / raw)
To: Jon Hunter
Cc: Thierry Reding, David S . Miller, Eric Dumazet, Paolo Abeni,
Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu, Rob Herring,
Krzysztof Kozlowski, Bhadram Varka, devicetree, linux-tegra,
netdev
On Thu, 22 Sep 2022 16:05:22 +0100 Jon Hunter wrote:
> On 07/09/2022 17:36, Thierry Reding wrote:
> > On Thu, Jul 07, 2022 at 09:48:18AM +0200, Thierry Reding wrote:
> >> From: Bhadram Varka <vbhadram@nvidia.com>
> >>
> >> Add support for the Multi-Gigabit Ethernet (MGBE/XPCS) IP found on
> >> NVIDIA Tegra234 SoCs.
> >>
> >> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
> >> Signed-off-by: Thierry Reding <treding@nvidia.com>
> >> ---
> >> Note that this doesn't have any dependencies on any of the patches
> >> earlier in the series, so this can be applied independently.
>
> > Patches 1-8 of this have already been applied to the Tegra tree. Are
> > there any more comments on this or can this be merged as well?
> >
> > From a Tegra point of view this looks good, so:
> >
> > Acked-by: Thierry Reding <treding@nvidia.com>
>
> Acked-by: Jon Hunter <jonathanh@nvidia.com>
>
> Please can we queue this for v6.1? I have added the stmmac maintainers
> to the email, but not sure if you can pick this up?
Could you repost it independently of the series so that it can go thru
the net auto-checkers? It should be able to make 6.1 pretty comfortably.
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH net-next v4 9/9] stmmac: tegra: Add MGBE support
2022-09-22 15:34 ` Jakub Kicinski
@ 2022-09-23 12:39 ` Thierry Reding
2022-09-23 12:52 ` Jakub Kicinski
0 siblings, 1 reply; 17+ messages in thread
From: Thierry Reding @ 2022-09-23 12:39 UTC (permalink / raw)
To: Jakub Kicinski
Cc: Jon Hunter, David S . Miller, Eric Dumazet, Paolo Abeni,
Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu, Rob Herring,
Krzysztof Kozlowski, Bhadram Varka, devicetree, linux-tegra,
netdev
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On Thu, Sep 22, 2022 at 08:34:54AM -0700, Jakub Kicinski wrote:
> On Thu, 22 Sep 2022 16:05:22 +0100 Jon Hunter wrote:
> > On 07/09/2022 17:36, Thierry Reding wrote:
> > > On Thu, Jul 07, 2022 at 09:48:18AM +0200, Thierry Reding wrote:
> > >> From: Bhadram Varka <vbhadram@nvidia.com>
> > >>
> > >> Add support for the Multi-Gigabit Ethernet (MGBE/XPCS) IP found on
> > >> NVIDIA Tegra234 SoCs.
> > >>
> > >> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
> > >> Signed-off-by: Thierry Reding <treding@nvidia.com>
> > >> ---
> > >> Note that this doesn't have any dependencies on any of the patches
> > >> earlier in the series, so this can be applied independently.
> >
> > > Patches 1-8 of this have already been applied to the Tegra tree. Are
> > > there any more comments on this or can this be merged as well?
> > >
> > > From a Tegra point of view this looks good, so:
> > >
> > > Acked-by: Thierry Reding <treding@nvidia.com>
> >
> > Acked-by: Jon Hunter <jonathanh@nvidia.com>
> >
> > Please can we queue this for v6.1? I have added the stmmac maintainers
> > to the email, but not sure if you can pick this up?
>
> Could you repost it independently of the series so that it can go thru
> the net auto-checkers? It should be able to make 6.1 pretty comfortably.
Done. Let me know if there's anything in the patch that needs more work.
For the auto-checkers, do they send out notifications if they find
anything or can I monitor them manually somewhere? Are all of those
reported in the patchwork checks?
Thierry
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH net-next v4 9/9] stmmac: tegra: Add MGBE support
2022-09-23 12:39 ` Thierry Reding
@ 2022-09-23 12:52 ` Jakub Kicinski
0 siblings, 0 replies; 17+ messages in thread
From: Jakub Kicinski @ 2022-09-23 12:52 UTC (permalink / raw)
To: Thierry Reding
Cc: Jon Hunter, David S . Miller, Eric Dumazet, Paolo Abeni,
Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu, Rob Herring,
Krzysztof Kozlowski, Bhadram Varka, devicetree, linux-tegra,
netdev
On Fri, 23 Sep 2022 14:39:49 +0200 Thierry Reding wrote:
> > Could you repost it independently of the series so that it can go thru
> > the net auto-checkers? It should be able to make 6.1 pretty comfortably.
>
> Done. Let me know if there's anything in the patch that needs more work.
> For the auto-checkers, do they send out notifications if they find
> anything or can I monitor them manually somewhere? Are all of those
> reported in the patchwork checks?
They are reported to patchwork, but they sometimes produce false
positives so we don't expect folks to look at the themselves. The
maintainers will reply to the submission and quote the failed checks
as needed.
Also note that we have a "at most one version per day" policy,
if, say, there is a build issue discovered please hold off posting
the new version for 24h. Frequent posting makes reviewing harder
for folks who read the list top to bottom and increases ML traffic.
^ permalink raw reply [flat|nested] 17+ messages in thread